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61619b1207
The changes in the mmu version of entry.h (entry_mm.h) and the non-mmu version (entry_no.h) are not about the presence or use of an MMU at all. The main changes are to support the ColdFire processors. The code for trap entry and exit for all types of 68k processor outside coldfire is the same. So merge the files back to a single entry.h and share the common 68k entry/exit code. Some changes are required for the non-mmu entry handlers to adopt the differing macros for system call and interrupt entry, but this is quite strait forward. The changes for the ColdFire remove a couple of instructions for the separate a7 register case, and are no worse for the older single a7 register case. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
203 lines
5.2 KiB
ArmAsm
203 lines
5.2 KiB
ArmAsm
/*
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* linux/arch/m68knommu/platform/5307/entry.S
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*
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* Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
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* Kenneth Albanowski <kjahds@kjahds.com>,
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* Copyright (C) 2000 Lineo Inc. (www.lineo.com)
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* Copyright (C) 2004-2006 Macq Electronique SA. (www.macqel.com)
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*
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* Based on:
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*
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* linux/arch/m68k/kernel/entry.S
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*
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* Copyright (C) 1991, 1992 Linus Torvalds
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file README.legal in the main directory of this archive
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* for more details.
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*
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* Linux/m68k support by Hamish Macdonald
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*
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* 68060 fixes by Jesper Skov
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* ColdFire support by Greg Ungerer (gerg@snapgear.com)
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* 5307 fixes by David W. Miller
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* linux 2.4 support David McCullough <davidm@snapgear.com>
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* Bug, speed and maintainability fixes by Philippe De Muyter <phdm@macqel.be>
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*/
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#include <linux/linkage.h>
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#include <asm/unistd.h>
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#include <asm/thread_info.h>
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#include <asm/errno.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/asm-offsets.h>
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#include <asm/entry.h>
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#ifdef CONFIG_COLDFIRE_SW_A7
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/*
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* Define software copies of the supervisor and user stack pointers.
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*/
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.bss
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sw_ksp:
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.long 0
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sw_usp:
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.long 0
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#endif /* CONFIG_COLDFIRE_SW_A7 */
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.text
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.globl system_call
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.globl resume
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.globl ret_from_exception
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.globl ret_from_signal
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.globl sys_call_table
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.globl inthandler
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.globl fasthandler
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enosys:
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mov.l #sys_ni_syscall,%d3
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bra 1f
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ENTRY(system_call)
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SAVE_ALL_SYS
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move #0x2000,%sr /* enable intrs again */
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cmpl #NR_syscalls,%d0
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jcc enosys
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lea sys_call_table,%a0
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lsll #2,%d0 /* movel %a0@(%d0:l:4),%d3 */
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movel %a0@(%d0),%d3
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jeq enosys
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1:
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movel %sp,%d2 /* get thread_info pointer */
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andl #-THREAD_SIZE,%d2 /* at start of kernel stack */
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movel %d2,%a0
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movel %a0@,%a1 /* save top of frame */
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movel %sp,%a1@(TASK_THREAD+THREAD_ESP0)
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btst #(TIF_SYSCALL_TRACE%8),%a0@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
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bnes 1f
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movel %d3,%a0
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jbsr %a0@
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movel %d0,%sp@(PT_OFF_D0) /* save the return value */
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jra ret_from_exception
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1:
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movel #-ENOSYS,%d2 /* strace needs -ENOSYS in PT_OFF_D0 */
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movel %d2,PT_OFF_D0(%sp) /* on syscall entry */
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subql #4,%sp
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SAVE_SWITCH_STACK
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jbsr syscall_trace_enter
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RESTORE_SWITCH_STACK
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addql #4,%sp
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movel %d3,%a0
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jbsr %a0@
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movel %d0,%sp@(PT_OFF_D0) /* save the return value */
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subql #4,%sp /* dummy return address */
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SAVE_SWITCH_STACK
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jbsr syscall_trace_leave
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ret_from_signal:
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RESTORE_SWITCH_STACK
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addql #4,%sp
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ret_from_exception:
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move #0x2700,%sr /* disable intrs */
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btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel */
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jeq Luser_return /* if so, skip resched, signals */
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#ifdef CONFIG_PREEMPT
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movel %sp,%d1 /* get thread_info pointer */
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andl #-THREAD_SIZE,%d1 /* at base of kernel stack */
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movel %d1,%a0
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movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
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andl #(1<<TIF_NEED_RESCHED),%d1
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jeq Lkernel_return
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movel %a0@(TINFO_PREEMPT),%d1
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cmpl #0,%d1
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jne Lkernel_return
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pea Lkernel_return
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jmp preempt_schedule_irq /* preempt the kernel */
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#endif
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Lkernel_return:
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moveml %sp@,%d1-%d5/%a0-%a2
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lea %sp@(32),%sp /* space for 8 regs */
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movel %sp@+,%d0
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addql #4,%sp /* orig d0 */
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addl %sp@+,%sp /* stk adj */
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rte
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Luser_return:
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movel %sp,%d1 /* get thread_info pointer */
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andl #-THREAD_SIZE,%d1 /* at base of kernel stack */
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movel %d1,%a0
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movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
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jne Lwork_to_do /* still work to do */
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Lreturn:
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RESTORE_USER
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Lwork_to_do:
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movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
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move #0x2000,%sr /* enable intrs again */
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btst #TIF_NEED_RESCHED,%d1
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jne reschedule
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/* GERG: do we need something here for TRACEing?? */
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Lsignal_return:
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subql #4,%sp /* dummy return address */
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SAVE_SWITCH_STACK
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pea %sp@(SWITCH_STACK_SIZE)
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jsr do_signal
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addql #4,%sp
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RESTORE_SWITCH_STACK
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addql #4,%sp
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jmp Luser_return
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/*
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* This is the generic interrupt handler (for all hardware interrupt
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* sources). Calls up to high level code to do all the work.
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*/
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ENTRY(inthandler)
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SAVE_ALL_INT
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movew %sp@(PT_OFF_FORMATVEC),%d0 /* put exception # in d0 */
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andl #0x03fc,%d0 /* mask out vector only */
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movel %sp,%sp@- /* push regs arg */
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lsrl #2,%d0 /* calculate real vector # */
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movel %d0,%sp@- /* push vector number */
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jbsr do_IRQ /* call high level irq handler */
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lea %sp@(8),%sp /* pop args off stack */
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bra ret_from_exception
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/*
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* Beware - when entering resume, prev (the current task) is
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* in a0, next (the new task) is in a1, so don't change these
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* registers until their contents are no longer needed.
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*/
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ENTRY(resume)
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movew %sr,%d1 /* save current status */
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movew %d1,%a0@(TASK_THREAD+THREAD_SR)
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movel %a0,%d1 /* get prev thread in d1 */
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SAVE_SWITCH_STACK
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movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack pointer */
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RDUSP /* movel %usp,%a3 */
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movel %a3,%a0@(TASK_THREAD+THREAD_USP) /* save thread user stack */
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movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore thread user stack */
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WRUSP /* movel %a3,%usp */
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movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new kernel stack */
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movew %a1@(TASK_THREAD+THREAD_SR),%d7 /* restore new status */
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movew %d7,%sr
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RESTORE_SWITCH_STACK
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rts
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