mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2bd7bc254a
This silences warnings like the following one when building with the latest binutils: arch/mips/kernel/genex.S: Assembler messages: arch/mips/kernel/genex.S:438: Warning: the `msa' extension requires 64-bit FPRs [ralf@linux-mips.org: Markos says binutils 2.25 and some 2.24 snapshots are affected.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9745/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
517 lines
11 KiB
C
517 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Ralf Baechle
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*/
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#ifndef _ASM_ASMMACRO_H
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#define _ASM_ASMMACRO_H
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#include <asm/hazards.h>
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#include <asm/asm-offsets.h>
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#include <asm/msa.h>
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#ifdef CONFIG_32BIT
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#include <asm/asmmacro-32.h>
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#endif
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#ifdef CONFIG_64BIT
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#include <asm/asmmacro-64.h>
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#endif
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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.macro local_irq_enable reg=t0
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ei
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irq_enable_hazard
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.endm
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.macro local_irq_disable reg=t0
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di
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irq_disable_hazard
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.endm
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#else
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.macro local_irq_enable reg=t0
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mfc0 \reg, CP0_STATUS
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ori \reg, \reg, 1
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mtc0 \reg, CP0_STATUS
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irq_enable_hazard
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.endm
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.macro local_irq_disable reg=t0
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#ifdef CONFIG_PREEMPT
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lw \reg, TI_PRE_COUNT($28)
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addi \reg, \reg, 1
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sw \reg, TI_PRE_COUNT($28)
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#endif
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mfc0 \reg, CP0_STATUS
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ori \reg, \reg, 1
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xori \reg, \reg, 1
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mtc0 \reg, CP0_STATUS
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irq_disable_hazard
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#ifdef CONFIG_PREEMPT
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lw \reg, TI_PRE_COUNT($28)
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addi \reg, \reg, -1
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sw \reg, TI_PRE_COUNT($28)
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#endif
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.endm
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#endif /* CONFIG_CPU_MIPSR2 */
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.macro fpu_save_16even thread tmp=t0
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.set push
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SET_HARDFLOAT
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cfc1 \tmp, fcr31
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sdc1 $f0, THREAD_FPR0(\thread)
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sdc1 $f2, THREAD_FPR2(\thread)
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sdc1 $f4, THREAD_FPR4(\thread)
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sdc1 $f6, THREAD_FPR6(\thread)
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sdc1 $f8, THREAD_FPR8(\thread)
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sdc1 $f10, THREAD_FPR10(\thread)
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sdc1 $f12, THREAD_FPR12(\thread)
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sdc1 $f14, THREAD_FPR14(\thread)
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sdc1 $f16, THREAD_FPR16(\thread)
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sdc1 $f18, THREAD_FPR18(\thread)
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sdc1 $f20, THREAD_FPR20(\thread)
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sdc1 $f22, THREAD_FPR22(\thread)
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sdc1 $f24, THREAD_FPR24(\thread)
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sdc1 $f26, THREAD_FPR26(\thread)
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sdc1 $f28, THREAD_FPR28(\thread)
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sdc1 $f30, THREAD_FPR30(\thread)
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sw \tmp, THREAD_FCR31(\thread)
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.set pop
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.endm
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.macro fpu_save_16odd thread
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.set push
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.set mips64r2
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SET_HARDFLOAT
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sdc1 $f1, THREAD_FPR1(\thread)
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sdc1 $f3, THREAD_FPR3(\thread)
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sdc1 $f5, THREAD_FPR5(\thread)
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sdc1 $f7, THREAD_FPR7(\thread)
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sdc1 $f9, THREAD_FPR9(\thread)
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sdc1 $f11, THREAD_FPR11(\thread)
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sdc1 $f13, THREAD_FPR13(\thread)
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sdc1 $f15, THREAD_FPR15(\thread)
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sdc1 $f17, THREAD_FPR17(\thread)
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sdc1 $f19, THREAD_FPR19(\thread)
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sdc1 $f21, THREAD_FPR21(\thread)
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sdc1 $f23, THREAD_FPR23(\thread)
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sdc1 $f25, THREAD_FPR25(\thread)
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sdc1 $f27, THREAD_FPR27(\thread)
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sdc1 $f29, THREAD_FPR29(\thread)
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sdc1 $f31, THREAD_FPR31(\thread)
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.set pop
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.endm
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.macro fpu_save_double thread status tmp
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
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defined(CONFIG_CPU_MIPS32_R6)
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sll \tmp, \status, 5
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bgez \tmp, 10f
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fpu_save_16odd \thread
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10:
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#endif
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fpu_save_16even \thread \tmp
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.endm
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.macro fpu_restore_16even thread tmp=t0
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.set push
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SET_HARDFLOAT
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lw \tmp, THREAD_FCR31(\thread)
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ldc1 $f0, THREAD_FPR0(\thread)
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ldc1 $f2, THREAD_FPR2(\thread)
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ldc1 $f4, THREAD_FPR4(\thread)
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ldc1 $f6, THREAD_FPR6(\thread)
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ldc1 $f8, THREAD_FPR8(\thread)
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ldc1 $f10, THREAD_FPR10(\thread)
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ldc1 $f12, THREAD_FPR12(\thread)
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ldc1 $f14, THREAD_FPR14(\thread)
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ldc1 $f16, THREAD_FPR16(\thread)
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ldc1 $f18, THREAD_FPR18(\thread)
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ldc1 $f20, THREAD_FPR20(\thread)
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ldc1 $f22, THREAD_FPR22(\thread)
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ldc1 $f24, THREAD_FPR24(\thread)
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ldc1 $f26, THREAD_FPR26(\thread)
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ldc1 $f28, THREAD_FPR28(\thread)
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ldc1 $f30, THREAD_FPR30(\thread)
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ctc1 \tmp, fcr31
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.endm
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.macro fpu_restore_16odd thread
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.set push
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.set mips64r2
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SET_HARDFLOAT
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ldc1 $f1, THREAD_FPR1(\thread)
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ldc1 $f3, THREAD_FPR3(\thread)
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ldc1 $f5, THREAD_FPR5(\thread)
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ldc1 $f7, THREAD_FPR7(\thread)
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ldc1 $f9, THREAD_FPR9(\thread)
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ldc1 $f11, THREAD_FPR11(\thread)
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ldc1 $f13, THREAD_FPR13(\thread)
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ldc1 $f15, THREAD_FPR15(\thread)
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ldc1 $f17, THREAD_FPR17(\thread)
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ldc1 $f19, THREAD_FPR19(\thread)
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ldc1 $f21, THREAD_FPR21(\thread)
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ldc1 $f23, THREAD_FPR23(\thread)
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ldc1 $f25, THREAD_FPR25(\thread)
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ldc1 $f27, THREAD_FPR27(\thread)
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ldc1 $f29, THREAD_FPR29(\thread)
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ldc1 $f31, THREAD_FPR31(\thread)
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.set pop
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.endm
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.macro fpu_restore_double thread status tmp
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
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defined(CONFIG_CPU_MIPS32_R6)
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sll \tmp, \status, 5
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bgez \tmp, 10f # 16 register mode?
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fpu_restore_16odd \thread
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10:
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#endif
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fpu_restore_16even \thread \tmp
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.endm
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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.macro _EXT rd, rs, p, s
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ext \rd, \rs, \p, \s
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.endm
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#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
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.macro _EXT rd, rs, p, s
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srl \rd, \rs, \p
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andi \rd, \rd, (1 << \s) - 1
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.endm
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#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
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/*
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* Temporary until all gas have MT ASE support
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*/
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.macro DMT reg=0
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.word 0x41600bc1 | (\reg << 16)
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.endm
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.macro EMT reg=0
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.word 0x41600be1 | (\reg << 16)
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.endm
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.macro DVPE reg=0
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.word 0x41600001 | (\reg << 16)
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.endm
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.macro EVPE reg=0
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.word 0x41600021 | (\reg << 16)
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.endm
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.macro MFTR rt=0, rd=0, u=0, sel=0
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.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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.macro MTTR rt=0, rd=0, u=0, sel=0
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.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
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.endm
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#ifdef TOOLCHAIN_SUPPORTS_MSA
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/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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#undef fp
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.macro _cfcmsa rd, cs
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.set push
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.set mips32r2
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.set fp=64
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.set msa
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cfcmsa \rd, $\cs
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.set pop
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.endm
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.macro _ctcmsa cd, rs
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.set push
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.set mips32r2
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.set fp=64
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.set msa
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ctcmsa $\cd, \rs
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.set pop
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.endm
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.macro ld_d wd, off, base
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.set push
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.set mips32r2
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.set fp=64
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.set msa
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ld.d $w\wd, \off(\base)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set mips32r2
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.set fp=64
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.set msa
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st.d $w\wd, \off(\base)
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.set pop
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.endm
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.macro copy_u_w ws, n
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.set push
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.set mips32r2
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.set fp=64
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.set msa
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copy_u.w $1, $w\ws[\n]
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.set pop
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.endm
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.macro copy_u_d ws, n
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.set push
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.set mips64r2
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.set fp=64
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.set msa
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copy_u.d $1, $w\ws[\n]
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.set pop
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.endm
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.macro insert_w wd, n
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.set push
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.set mips32r2
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.set fp=64
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.set msa
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insert.w $w\wd[\n], $1
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.set pop
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.endm
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.macro insert_d wd, n
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.set push
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.set mips64r2
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.set fp=64
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.set msa
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insert.d $w\wd[\n], $1
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.set pop
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.endm
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#else
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#ifdef CONFIG_CPU_MICROMIPS
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#define CFC_MSA_INSN 0x587e0056
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#define CTC_MSA_INSN 0x583e0816
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#define LDD_MSA_INSN 0x58000837
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#define STD_MSA_INSN 0x5800083f
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#define COPY_UW_MSA_INSN 0x58f00056
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#define COPY_UD_MSA_INSN 0x58f80056
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#define INSERT_W_MSA_INSN 0x59300816
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#define INSERT_D_MSA_INSN 0x59380816
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#else
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#define CFC_MSA_INSN 0x787e0059
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#define CTC_MSA_INSN 0x783e0819
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#define LDD_MSA_INSN 0x78000823
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#define STD_MSA_INSN 0x78000827
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#define COPY_UW_MSA_INSN 0x78f00059
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#define COPY_UD_MSA_INSN 0x78f80059
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#define INSERT_W_MSA_INSN 0x79300819
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#define INSERT_D_MSA_INSN 0x79380819
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#endif
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/*
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* Temporary until all toolchains in use include MSA support.
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*/
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.macro _cfcmsa rd, cs
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.set push
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.set noat
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SET_HARDFLOAT
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.insn
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.word CFC_MSA_INSN | (\cs << 11)
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move \rd, $1
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.set pop
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.endm
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.macro _ctcmsa cd, rs
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.set push
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.set noat
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SET_HARDFLOAT
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move $1, \rs
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.word CTC_MSA_INSN | (\cd << 6)
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.set pop
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.endm
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.macro ld_d wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word LDD_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word STD_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro copy_u_w ws, n
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.set push
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.set noat
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SET_HARDFLOAT
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.insn
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.word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
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.set pop
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.endm
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.macro copy_u_d ws, n
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.set push
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.set noat
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SET_HARDFLOAT
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.insn
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.word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
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.set pop
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.endm
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.macro insert_w wd, n
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.set push
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.set noat
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SET_HARDFLOAT
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.word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
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.set pop
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.endm
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.macro insert_d wd, n
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.set push
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.set noat
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SET_HARDFLOAT
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.word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
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.set pop
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.endm
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#endif
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.macro msa_save_all thread
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st_d 0, THREAD_FPR0, \thread
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st_d 1, THREAD_FPR1, \thread
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st_d 2, THREAD_FPR2, \thread
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st_d 3, THREAD_FPR3, \thread
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st_d 4, THREAD_FPR4, \thread
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st_d 5, THREAD_FPR5, \thread
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st_d 6, THREAD_FPR6, \thread
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st_d 7, THREAD_FPR7, \thread
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st_d 8, THREAD_FPR8, \thread
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st_d 9, THREAD_FPR9, \thread
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st_d 10, THREAD_FPR10, \thread
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st_d 11, THREAD_FPR11, \thread
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st_d 12, THREAD_FPR12, \thread
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st_d 13, THREAD_FPR13, \thread
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st_d 14, THREAD_FPR14, \thread
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st_d 15, THREAD_FPR15, \thread
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st_d 16, THREAD_FPR16, \thread
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st_d 17, THREAD_FPR17, \thread
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st_d 18, THREAD_FPR18, \thread
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st_d 19, THREAD_FPR19, \thread
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st_d 20, THREAD_FPR20, \thread
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st_d 21, THREAD_FPR21, \thread
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st_d 22, THREAD_FPR22, \thread
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st_d 23, THREAD_FPR23, \thread
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st_d 24, THREAD_FPR24, \thread
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st_d 25, THREAD_FPR25, \thread
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st_d 26, THREAD_FPR26, \thread
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st_d 27, THREAD_FPR27, \thread
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st_d 28, THREAD_FPR28, \thread
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st_d 29, THREAD_FPR29, \thread
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st_d 30, THREAD_FPR30, \thread
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st_d 31, THREAD_FPR31, \thread
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.set push
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.set noat
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SET_HARDFLOAT
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_cfcmsa $1, MSA_CSR
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sw $1, THREAD_MSA_CSR(\thread)
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.set pop
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.endm
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.macro msa_restore_all thread
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.set push
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.set noat
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SET_HARDFLOAT
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lw $1, THREAD_MSA_CSR(\thread)
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_ctcmsa MSA_CSR, $1
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.set pop
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ld_d 0, THREAD_FPR0, \thread
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ld_d 1, THREAD_FPR1, \thread
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ld_d 2, THREAD_FPR2, \thread
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ld_d 3, THREAD_FPR3, \thread
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ld_d 4, THREAD_FPR4, \thread
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ld_d 5, THREAD_FPR5, \thread
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ld_d 6, THREAD_FPR6, \thread
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ld_d 7, THREAD_FPR7, \thread
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ld_d 8, THREAD_FPR8, \thread
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ld_d 9, THREAD_FPR9, \thread
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ld_d 10, THREAD_FPR10, \thread
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ld_d 11, THREAD_FPR11, \thread
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ld_d 12, THREAD_FPR12, \thread
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ld_d 13, THREAD_FPR13, \thread
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ld_d 14, THREAD_FPR14, \thread
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ld_d 15, THREAD_FPR15, \thread
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ld_d 16, THREAD_FPR16, \thread
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ld_d 17, THREAD_FPR17, \thread
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ld_d 18, THREAD_FPR18, \thread
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ld_d 19, THREAD_FPR19, \thread
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ld_d 20, THREAD_FPR20, \thread
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ld_d 21, THREAD_FPR21, \thread
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ld_d 22, THREAD_FPR22, \thread
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ld_d 23, THREAD_FPR23, \thread
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ld_d 24, THREAD_FPR24, \thread
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ld_d 25, THREAD_FPR25, \thread
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ld_d 26, THREAD_FPR26, \thread
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ld_d 27, THREAD_FPR27, \thread
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ld_d 28, THREAD_FPR28, \thread
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ld_d 29, THREAD_FPR29, \thread
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ld_d 30, THREAD_FPR30, \thread
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ld_d 31, THREAD_FPR31, \thread
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.endm
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|
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.macro msa_init_upper wd
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|
#ifdef CONFIG_64BIT
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|
insert_d \wd, 1
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#else
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insert_w \wd, 2
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|
insert_w \wd, 3
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#endif
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|
.endm
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|
|
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.macro msa_init_all_upper
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|
.set push
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|
.set noat
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|
SET_HARDFLOAT
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|
not $1, zero
|
|
msa_init_upper 0
|
|
msa_init_upper 1
|
|
msa_init_upper 2
|
|
msa_init_upper 3
|
|
msa_init_upper 4
|
|
msa_init_upper 5
|
|
msa_init_upper 6
|
|
msa_init_upper 7
|
|
msa_init_upper 8
|
|
msa_init_upper 9
|
|
msa_init_upper 10
|
|
msa_init_upper 11
|
|
msa_init_upper 12
|
|
msa_init_upper 13
|
|
msa_init_upper 14
|
|
msa_init_upper 15
|
|
msa_init_upper 16
|
|
msa_init_upper 17
|
|
msa_init_upper 18
|
|
msa_init_upper 19
|
|
msa_init_upper 20
|
|
msa_init_upper 21
|
|
msa_init_upper 22
|
|
msa_init_upper 23
|
|
msa_init_upper 24
|
|
msa_init_upper 25
|
|
msa_init_upper 26
|
|
msa_init_upper 27
|
|
msa_init_upper 28
|
|
msa_init_upper 29
|
|
msa_init_upper 30
|
|
msa_init_upper 31
|
|
.set pop
|
|
.endm
|
|
|
|
#endif /* _ASM_ASMMACRO_H */
|