mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 00:47:22 +07:00
d908175cca
The regs belong to PFIFO, they're different for pretty much the same generations we need different PFIFO control for, and NVC0 is going to be even more different than the rest. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
247 lines
7.8 KiB
C
247 lines
7.8 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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#define NV10_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV10_RAMFC__SIZE))
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#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
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int
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nv10_fifo_channel_id(struct drm_device *dev)
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{
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return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
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NV10_PFIFO_CACHE1_PUSH1_CHID_MASK;
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}
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int
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nv10_fifo_create_context(struct nouveau_channel *chan)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct drm_device *dev = chan->dev;
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uint32_t fc = NV10_RAMFC(chan->id);
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int ret;
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ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
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NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
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if (ret)
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return ret;
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chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
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NV03_USER(chan->id), PAGE_SIZE);
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if (!chan->user)
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return -ENOMEM;
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/* Fill entries that are seen filled in dumps of nvidia driver just
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* after channel's is put into DMA mode
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*/
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nv_wi32(dev, fc + 0, chan->pushbuf_base);
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nv_wi32(dev, fc + 4, chan->pushbuf_base);
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nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
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nv_wi32(dev, fc + 20, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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0);
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/* enable the fifo dma operation */
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nv_wr32(dev, NV04_PFIFO_MODE,
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nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
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return 0;
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}
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static void
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nv10_fifo_do_load_context(struct drm_device *dev, int chid)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t fc = NV10_RAMFC(chid), tmp;
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
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nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
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tmp = nv_ri32(dev, fc + 12);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 16));
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 20));
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nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 24));
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 28));
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if (dev_priv->chipset < 0x17)
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goto out;
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nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 32));
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tmp = nv_ri32(dev, fc + 36);
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nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
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nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 40));
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nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 44));
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nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 48));
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out:
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
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}
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int
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nv10_fifo_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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uint32_t tmp;
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nv10_fifo_do_load_context(dev, chan->id);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
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NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
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/* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
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tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
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nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
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return 0;
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}
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int
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nv10_fifo_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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uint32_t fc, tmp;
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int chid;
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chid = pfifo->channel_id(dev);
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if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
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return 0;
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fc = NV10_RAMFC(chid);
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nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
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nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
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nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
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tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
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tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
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nv_wi32(dev, fc + 12, tmp);
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nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
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nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
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nv_wi32(dev, fc + 24, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
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nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
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if (dev_priv->chipset < 0x17)
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goto out;
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nv_wi32(dev, fc + 32, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
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tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
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nv_wi32(dev, fc + 36, tmp);
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nv_wi32(dev, fc + 40, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
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nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
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nv_wi32(dev, fc + 48, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
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out:
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nv10_fifo_do_load_context(dev, pfifo->channels - 1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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return 0;
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}
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static void
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nv10_fifo_init_reset(struct drm_device *dev)
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{
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nv_wr32(dev, NV03_PMC_ENABLE,
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nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
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nv_wr32(dev, NV03_PMC_ENABLE,
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nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO);
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nv_wr32(dev, 0x003224, 0x000f0078);
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nv_wr32(dev, 0x002044, 0x0101ffff);
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nv_wr32(dev, 0x002040, 0x000000ff);
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nv_wr32(dev, 0x002500, 0x00000000);
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nv_wr32(dev, 0x003000, 0x00000000);
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nv_wr32(dev, 0x003050, 0x00000000);
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nv_wr32(dev, 0x003258, 0x00000000);
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nv_wr32(dev, 0x003210, 0x00000000);
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nv_wr32(dev, 0x003270, 0x00000000);
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}
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static void
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nv10_fifo_init_ramxx(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
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((dev_priv->ramht->bits - 9) << 16) |
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(dev_priv->ramht->gpuobj->pinst >> 8));
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nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
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if (dev_priv->chipset < 0x17) {
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nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8);
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} else {
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nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc->pinst >> 8) |
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(1 << 16) /* 64 Bytes entry*/);
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/* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
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}
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}
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static void
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nv10_fifo_init_intr(struct drm_device *dev)
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{
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nouveau_irq_register(dev, 8, nv04_fifo_isr);
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nv_wr32(dev, 0x002100, 0xffffffff);
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nv_wr32(dev, 0x002140, 0xffffffff);
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}
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int
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nv10_fifo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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int i;
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nv10_fifo_init_reset(dev);
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nv10_fifo_init_ramxx(dev);
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nv10_fifo_do_load_context(dev, pfifo->channels - 1);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
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nv10_fifo_init_intr(dev);
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pfifo->enable(dev);
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pfifo->reassign(dev, true);
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for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
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if (dev_priv->channels.ptr[i]) {
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uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
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nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
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}
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}
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return 0;
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}
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