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a3ac3d4a29
According to the technical update (No. TN-RCS-B011A/E), the UGSTS LOCK bit location is bit 8, not bits 1 and 0. It also says that the register address offset of UGSTS is 0x88, not 0x90. So, this patch fixes the USBHS_UGSTS_LOCK value and some comments. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| phy-armada375-usb2.c | ||
| phy-bcm-kona-usb2.c | ||
| phy-berlin-sata.c | ||
| phy-berlin-usb.c | ||
| phy-core.c | ||
| phy-dm816x-usb.c | ||
| phy-exynos4x12-usb2.c | ||
| phy-exynos5-usbdrd.c | ||
| phy-exynos4210-usb2.c | ||
| phy-exynos5250-sata.c | ||
| phy-exynos5250-usb2.c | ||
| phy-exynos-dp-video.c | ||
| phy-exynos-mipi-video.c | ||
| phy-hix5hd2-sata.c | ||
| phy-miphy28lp.c | ||
| phy-miphy365x.c | ||
| phy-mvebu-sata.c | ||
| phy-omap-control.c | ||
| phy-omap-usb2.c | ||
| phy-qcom-apq8064-sata.c | ||
| phy-qcom-ipq806x-sata.c | ||
| phy-qcom-ufs-i.h | ||
| phy-qcom-ufs-qmp-14nm.c | ||
| phy-qcom-ufs-qmp-14nm.h | ||
| phy-qcom-ufs-qmp-20nm.c | ||
| phy-qcom-ufs-qmp-20nm.h | ||
| phy-qcom-ufs.c | ||
| phy-rcar-gen2.c | ||
| phy-rockchip-usb.c | ||
| phy-s5pv210-usb2.c | ||
| phy-samsung-usb2.c | ||
| phy-samsung-usb2.h | ||
| phy-spear1310-miphy.c | ||
| phy-spear1340-miphy.c | ||
| phy-stih41x-usb.c | ||
| phy-stih407-usb.c | ||
| phy-sun4i-usb.c | ||
| phy-sun9i-usb.c | ||
| phy-ti-pipe3.c | ||
| phy-twl4030-usb.c | ||
| phy-xgene.c | ||