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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d61dd248dd
Do not need to maintain our own shmem memory management code as drm_gem_shmem_helpers provides it. And we can also benifit from the work of others with shared code. This is also a preparation for implementing buffer madv. Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191010140152.17747-2-yuq825@gmail.com
142 lines
3.8 KiB
C
142 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/device.h>
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#include "lima_device.h"
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#include "lima_mmu.h"
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#include "lima_vm.h"
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#include "lima_regs.h"
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#define mmu_write(reg, data) writel(data, ip->iomem + reg)
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#define mmu_read(reg) readl(ip->iomem + reg)
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#define lima_mmu_send_command(cmd, addr, val, cond) \
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({ \
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int __ret; \
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\
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mmu_write(LIMA_MMU_COMMAND, cmd); \
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__ret = readl_poll_timeout(ip->iomem + (addr), val, \
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cond, 0, 100); \
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if (__ret) \
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dev_err(dev->dev, \
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"mmu command %x timeout\n", cmd); \
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__ret; \
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})
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static irqreturn_t lima_mmu_irq_handler(int irq, void *data)
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{
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struct lima_ip *ip = data;
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struct lima_device *dev = ip->dev;
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u32 status = mmu_read(LIMA_MMU_INT_STATUS);
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struct lima_sched_pipe *pipe;
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/* for shared irq case */
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if (!status)
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return IRQ_NONE;
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if (status & LIMA_MMU_INT_PAGE_FAULT) {
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u32 fault = mmu_read(LIMA_MMU_PAGE_FAULT_ADDR);
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dev_err(dev->dev, "mmu page fault at 0x%x from bus id %d of type %s on %s\n",
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fault, LIMA_MMU_STATUS_BUS_ID(status),
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status & LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE ? "write" : "read",
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lima_ip_name(ip));
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}
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if (status & LIMA_MMU_INT_READ_BUS_ERROR)
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dev_err(dev->dev, "mmu %s irq bus error\n", lima_ip_name(ip));
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/* mask all interrupts before resume */
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mmu_write(LIMA_MMU_INT_MASK, 0);
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mmu_write(LIMA_MMU_INT_CLEAR, status);
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pipe = dev->pipe + (ip->id == lima_ip_gpmmu ? lima_pipe_gp : lima_pipe_pp);
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lima_sched_pipe_mmu_error(pipe);
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return IRQ_HANDLED;
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}
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int lima_mmu_init(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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int err;
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u32 v;
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if (ip->id == lima_ip_ppmmu_bcast)
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return 0;
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mmu_write(LIMA_MMU_DTE_ADDR, 0xCAFEBABE);
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if (mmu_read(LIMA_MMU_DTE_ADDR) != 0xCAFEB000) {
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dev_err(dev->dev, "mmu %s dte write test fail\n", lima_ip_name(ip));
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return -EIO;
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}
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mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_HARD_RESET);
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err = lima_mmu_send_command(LIMA_MMU_COMMAND_HARD_RESET,
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LIMA_MMU_DTE_ADDR, v, v == 0);
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if (err)
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return err;
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err = devm_request_irq(dev->dev, ip->irq, lima_mmu_irq_handler,
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IRQF_SHARED, lima_ip_name(ip), ip);
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if (err) {
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dev_err(dev->dev, "mmu %s fail to request irq\n", lima_ip_name(ip));
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return err;
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}
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mmu_write(LIMA_MMU_INT_MASK, LIMA_MMU_INT_PAGE_FAULT | LIMA_MMU_INT_READ_BUS_ERROR);
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mmu_write(LIMA_MMU_DTE_ADDR, dev->empty_vm->pd.dma);
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return lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_PAGING,
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LIMA_MMU_STATUS, v,
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v & LIMA_MMU_STATUS_PAGING_ENABLED);
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}
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void lima_mmu_fini(struct lima_ip *ip)
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{
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}
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void lima_mmu_switch_vm(struct lima_ip *ip, struct lima_vm *vm)
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{
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struct lima_device *dev = ip->dev;
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u32 v;
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lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_STALL,
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LIMA_MMU_STATUS, v,
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v & LIMA_MMU_STATUS_STALL_ACTIVE);
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if (vm)
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mmu_write(LIMA_MMU_DTE_ADDR, vm->pd.dma);
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/* flush the TLB */
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mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_ZAP_CACHE);
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lima_mmu_send_command(LIMA_MMU_COMMAND_DISABLE_STALL,
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LIMA_MMU_STATUS, v,
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!(v & LIMA_MMU_STATUS_STALL_ACTIVE));
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}
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void lima_mmu_page_fault_resume(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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u32 status = mmu_read(LIMA_MMU_STATUS);
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u32 v;
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if (status & LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE) {
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dev_info(dev->dev, "mmu resume\n");
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mmu_write(LIMA_MMU_INT_MASK, 0);
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mmu_write(LIMA_MMU_DTE_ADDR, 0xCAFEBABE);
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lima_mmu_send_command(LIMA_MMU_COMMAND_HARD_RESET,
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LIMA_MMU_DTE_ADDR, v, v == 0);
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mmu_write(LIMA_MMU_INT_MASK, LIMA_MMU_INT_PAGE_FAULT | LIMA_MMU_INT_READ_BUS_ERROR);
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mmu_write(LIMA_MMU_DTE_ADDR, dev->empty_vm->pd.dma);
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lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_PAGING,
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LIMA_MMU_STATUS, v,
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v & LIMA_MMU_STATUS_PAGING_ENABLED);
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}
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}
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