mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 11:55:49 +07:00
01f52e16b8
pfn_to_page & page_to_pfn depend on vmemmap being available before the calls
if kernel is configured with CONFIG_SPARSEMEM_VMEMMAP=y. This was caused
by NOMMU changes which moved vmemmap definition bellow functions definitions
calling pfn_to_page & page_to_pfn.
Noticed while compiled 5.5-rc2 kernel for Fedora/RISCV.
v2:
- Add a comment for vmemmap in source
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Fixes: 6bd33e1ece ("riscv: add nommu support")
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
476 lines
12 KiB
C
476 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_PGTABLE_H
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#define _ASM_RISCV_PGTABLE_H
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#include <linux/mmzone.h>
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#include <linux/sizes.h>
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#include <asm/pgtable-bits.h>
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#ifndef __ASSEMBLY__
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/* Page Upper Directory not used in RISC-V */
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#include <asm-generic/pgtable-nopud.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include <linux/mm_types.h>
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#ifdef CONFIG_64BIT
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#include <asm/pgtable-64.h>
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#else
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#include <asm/pgtable-32.h>
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#endif /* CONFIG_64BIT */
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#ifdef CONFIG_MMU
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/* Number of entries in the page global directory */
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#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
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/* Number of entries in the page table */
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#define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t))
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/* Number of PGD entries that a user-mode program can use */
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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/* Page protection bits */
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#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER)
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#define PAGE_NONE __pgprot(_PAGE_PROT_NONE)
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#define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ)
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#define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE)
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#define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC)
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#define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
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#define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \
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_PAGE_EXEC | _PAGE_WRITE)
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#define PAGE_COPY PAGE_READ
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#define PAGE_COPY_EXEC PAGE_EXEC
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#define PAGE_COPY_READ_EXEC PAGE_READ_EXEC
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#define PAGE_SHARED PAGE_WRITE
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#define PAGE_SHARED_EXEC PAGE_WRITE_EXEC
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#define _PAGE_KERNEL (_PAGE_READ \
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| _PAGE_WRITE \
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| _PAGE_PRESENT \
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| _PAGE_ACCESSED \
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| _PAGE_DIRTY)
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#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC)
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#define PAGE_TABLE __pgprot(_PAGE_TABLE)
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/*
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* The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
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* change the properties of memory regions.
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*/
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#define _PAGE_IOREMAP _PAGE_KERNEL
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extern pgd_t swapper_pg_dir[];
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/* MAP_PRIVATE permissions: xwr (copy-on-write) */
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READ
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_EXEC
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#define __P101 PAGE_READ_EXEC
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#define __P110 PAGE_COPY_EXEC
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#define __P111 PAGE_COPY_READ_EXEC
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/* MAP_SHARED permissions: xwr */
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READ
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_EXEC
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#define __S101 PAGE_READ_EXEC
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#define __S110 PAGE_SHARED_EXEC
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#define __S111 PAGE_SHARED_EXEC
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#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
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#define VMALLOC_END (PAGE_OFFSET - 1)
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#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
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/*
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* Roughly size the vmemmap space to be large enough to fit enough
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* struct pages to map half the virtual address space. Then
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* position vmemmap directly below the VMALLOC region.
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*/
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#define VMEMMAP_SHIFT \
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(CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT)
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#define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT)
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#define VMEMMAP_END (VMALLOC_START - 1)
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#define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE)
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/*
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* Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel
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* is configured with CONFIG_SPARSEMEM_VMEMMAP enabled.
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*/
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#define vmemmap ((struct page *)VMEMMAP_START)
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static inline int pmd_present(pmd_t pmd)
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{
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return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
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}
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static inline int pmd_none(pmd_t pmd)
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{
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return (pmd_val(pmd) == 0);
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}
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static inline int pmd_bad(pmd_t pmd)
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{
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return !pmd_present(pmd);
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}
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static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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*pmdp = pmd;
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}
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static inline void pmd_clear(pmd_t *pmdp)
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{
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set_pmd(pmdp, __pmd(0));
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}
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static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
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{
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return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
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}
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static inline unsigned long _pgd_pfn(pgd_t pgd)
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{
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return pgd_val(pgd) >> _PAGE_PFN_SHIFT;
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}
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#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
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/* Locate an entry in the page global directory */
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static inline pgd_t *pgd_offset(const struct mm_struct *mm, unsigned long addr)
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{
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return mm->pgd + pgd_index(addr);
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}
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/* Locate an entry in the kernel page global directory */
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#define pgd_offset_k(addr) pgd_offset(&init_mm, (addr))
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static inline struct page *pmd_page(pmd_t pmd)
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{
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return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
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}
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static inline unsigned long pmd_page_vaddr(pmd_t pmd)
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{
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return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
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}
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/* Yields the page frame number (PFN) of a page table entry */
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static inline unsigned long pte_pfn(pte_t pte)
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{
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return (pte_val(pte) >> _PAGE_PFN_SHIFT);
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}
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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/* Constructs a page table entry */
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
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{
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return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
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}
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#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
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#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long addr)
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{
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return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(addr);
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}
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#define pte_offset_map(dir, addr) pte_offset_kernel((dir), (addr))
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#define pte_unmap(pte) ((void)(pte))
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static inline int pte_present(pte_t pte)
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{
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return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
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}
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static inline int pte_none(pte_t pte)
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{
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return (pte_val(pte) == 0);
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}
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static inline int pte_write(pte_t pte)
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{
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return pte_val(pte) & _PAGE_WRITE;
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}
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static inline int pte_exec(pte_t pte)
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{
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return pte_val(pte) & _PAGE_EXEC;
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}
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static inline int pte_huge(pte_t pte)
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{
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return pte_present(pte)
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&& (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC));
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}
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static inline int pte_dirty(pte_t pte)
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{
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return pte_val(pte) & _PAGE_DIRTY;
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}
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static inline int pte_young(pte_t pte)
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{
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return pte_val(pte) & _PAGE_ACCESSED;
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}
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static inline int pte_special(pte_t pte)
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{
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return pte_val(pte) & _PAGE_SPECIAL;
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}
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/* static inline pte_t pte_rdprotect(pte_t pte) */
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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return __pte(pte_val(pte) & ~(_PAGE_WRITE));
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}
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/* static inline pte_t pte_mkread(pte_t pte) */
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_WRITE);
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}
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/* static inline pte_t pte_mkexec(pte_t pte) */
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_DIRTY);
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return __pte(pte_val(pte) & ~(_PAGE_DIRTY));
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_ACCESSED);
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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return __pte(pte_val(pte) & ~(_PAGE_ACCESSED));
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}
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static inline pte_t pte_mkspecial(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SPECIAL);
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}
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static inline pte_t pte_mkhuge(pte_t pte)
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{
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return pte;
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}
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/* Modify page protection bits */
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e))
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/* Commit new configuration to MMU hardware */
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep)
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{
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/*
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* The kernel assumes that TLBs don't cache invalid entries, but
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* in RISC-V, SFENCE.VMA specifies an ordering constraint, not a
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* cache flush; it is necessary even after writing invalid entries.
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* Relying on flush_tlb_fix_spurious_fault would suffice, but
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* the extra traps reduce performance. So, eagerly SFENCE.VMA.
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*/
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local_flush_tlb_page(address);
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}
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#define __HAVE_ARCH_PTE_SAME
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static inline int pte_same(pte_t pte_a, pte_t pte_b)
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{
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return pte_val(pte_a) == pte_val(pte_b);
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}
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/*
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* Certain architectures need to do special things when PTEs within
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* a page table are directly modified. Thus, the following hook is
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* made available.
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*/
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static inline void set_pte(pte_t *ptep, pte_t pteval)
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{
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*ptep = pteval;
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}
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void flush_icache_pte(pte_t pte);
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static inline void set_pte_at(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep, pte_t pteval)
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{
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if (pte_present(pteval) && pte_exec(pteval))
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flush_icache_pte(pteval);
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set_pte(ptep, pteval);
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}
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static inline void pte_clear(struct mm_struct *mm,
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unsigned long addr, pte_t *ptep)
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{
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set_pte_at(mm, addr, ptep, __pte(0));
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}
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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static inline int ptep_set_access_flags(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep,
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pte_t entry, int dirty)
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{
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if (!pte_same(*ptep, entry))
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set_pte_at(vma->vm_mm, address, ptep, entry);
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/*
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* update_mmu_cache will unconditionally execute, handling both
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* the case that the PTE changed and the spurious fault case.
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*/
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return true;
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}
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
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unsigned long address, pte_t *ptep)
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{
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return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0));
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}
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
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unsigned long address,
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pte_t *ptep)
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{
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if (!pte_young(*ptep))
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return 0;
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return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep));
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}
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm,
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unsigned long address, pte_t *ptep)
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{
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atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep);
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}
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#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
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static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep)
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{
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/*
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* This comment is borrowed from x86, but applies equally to RISC-V:
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*
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* Clearing the accessed bit without a TLB flush
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* doesn't cause data corruption. [ It could cause incorrect
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* page aging and the (mistaken) reclaim of hot pages, but the
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* chance of that should be relatively low. ]
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*
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* So as a performance optimization don't flush the TLB when
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* clearing the accessed bit, it will eventually be flushed by
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* a context switch or a VM operation anyway. [ In the rare
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* event of it not getting flushed for a long time the delay
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* shouldn't really matter because there's no real memory
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* pressure for swapout to react to. ]
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*/
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return ptep_test_and_clear_young(vma, address, ptep);
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}
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/*
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* Encode and decode a swap entry
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*
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* Format of swap PTE:
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* bit 0: _PAGE_PRESENT (zero)
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* bit 1: _PAGE_PROT_NONE (zero)
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* bits 2 to 6: swap type
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* bits 7 to XLEN-1: swap offset
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*/
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#define __SWP_TYPE_SHIFT 2
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#define __SWP_TYPE_BITS 5
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#define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1)
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#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
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#define MAX_SWAPFILES_CHECK() \
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BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
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#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
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#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
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#define __swp_entry(type, offset) ((swp_entry_t) \
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{ ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define PCI_IO_SIZE SZ_16M
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#define PCI_IO_END VMEMMAP_START
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#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
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#define FIXADDR_TOP PCI_IO_START
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#ifdef CONFIG_64BIT
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#define FIXADDR_SIZE PMD_SIZE
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#else
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#define FIXADDR_SIZE PGDIR_SIZE
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#endif
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#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
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/*
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* Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
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* Note that PGDIR_SIZE must evenly divide TASK_SIZE.
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*/
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#ifdef CONFIG_64BIT
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#define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2)
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#else
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#define TASK_SIZE FIXADDR_START
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#endif
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#else /* CONFIG_MMU */
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#define PAGE_KERNEL __pgprot(0)
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#define swapper_pg_dir NULL
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#define VMALLOC_START 0
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#define TASK_SIZE 0xffffffffUL
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#endif /* !CONFIG_MMU */
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#define kern_addr_valid(addr) (1) /* FIXME */
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extern void *dtb_early_va;
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void setup_bootmem(void);
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void paging_init(void);
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#define FIRST_USER_ADDRESS 0
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/*
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* ZERO_PAGE is a global shared page that is always zero,
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* used for zero-mapped memory areas, etc.
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*/
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extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#include <asm-generic/pgtable.h>
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_RISCV_PGTABLE_H */
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