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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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173d668138
The Xtensa port contained many header files that were never needed. This rather lengthy patch removes all those files. Unfortunately, there were many dependencies that needed to be updated, so this patch touches quite a few source files. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
123 lines
3.5 KiB
C
123 lines
3.5 KiB
C
/*
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* include/asm-xtensa/cacheflush.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) 2001 - 2006 Tensilica Inc.
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*/
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#ifndef _XTENSA_CACHEFLUSH_H
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#define _XTENSA_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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/*
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* flush and invalidate data cache, invalidate instruction cache:
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*
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* __flush_invalidate_cache_all()
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* __flush_invalidate_cache_range(from,sze)
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*
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* invalidate data or instruction cache:
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*
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* __invalidate_icache_all()
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* __invalidate_icache_page(adr)
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* __invalidate_dcache_page(adr)
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* __invalidate_icache_range(from,size)
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* __invalidate_dcache_range(from,size)
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*
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* flush data cache:
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*
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* __flush_dcache_page(adr)
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*
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* flush and invalidate data cache:
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*
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* __flush_invalidate_dcache_all()
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* __flush_invalidate_dcache_page(adr)
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* __flush_invalidate_dcache_range(from,size)
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*/
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extern void __flush_invalidate_cache_all(void);
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extern void __flush_invalidate_cache_range(unsigned long, unsigned long);
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extern void __flush_invalidate_dcache_all(void);
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extern void __invalidate_icache_all(void);
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extern void __invalidate_dcache_page(unsigned long);
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extern void __invalidate_icache_page(unsigned long);
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extern void __invalidate_icache_range(unsigned long, unsigned long);
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extern void __invalidate_dcache_range(unsigned long, unsigned long);
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#if XCHAL_DCACHE_IS_WRITEBACK
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extern void __flush_dcache_page(unsigned long);
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extern void __flush_invalidate_dcache_page(unsigned long);
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extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
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#else
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# define __flush_dcache_page(p) do { } while(0)
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# define __flush_invalidate_dcache_page(p) do { } while(0)
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# define __flush_invalidate_dcache_range(p,s) do { } while(0)
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#endif
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/*
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* We have physically tagged caches - nothing to do here -
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* unless we have cache aliasing.
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*
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* Pages can get remapped. Because this might change the 'color' of that page,
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* we have to flush the cache before the PTE is changed.
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* (see also Documentation/cachetlb.txt)
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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#define flush_cache_all() __flush_invalidate_cache_all();
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#define flush_cache_mm(mm) __flush_invalidate_cache_all();
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#define flush_cache_vmap(start,end) __flush_invalidate_cache_all();
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#define flush_cache_vunmap(start,end) __flush_invalidate_cache_all();
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extern void flush_dcache_page(struct page*);
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extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
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extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
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#else
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_vmap(start,end) do { } while (0)
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#define flush_cache_vunmap(start,end) do { } while (0)
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#define flush_dcache_page(page) do { } while (0)
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#define flush_cache_page(vma,addr,pfn) do { } while (0)
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#define flush_cache_range(vma,start,end) do { } while (0)
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#endif
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#define flush_icache_range(start,end) \
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__invalidate_icache_range(start,(end)-(start))
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/* This is not required, see Documentation/cachetlb.txt */
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#define flush_icache_page(vma,page) do { } while(0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_CACHEFLUSH_H */
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