mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 21:40:52 +07:00
d9f18a981b
This patch adds IRQ support for S5P6442. This patch adds interrupt register definitions, IRQ definitions for various interrupt sources and new VIC base for VIC2 in plat-s5p common irq code. Signed-off-by: Adityapratap Sharma <aditya.ps@samsung.com> Signed-off-by: Atul Dahiya <atul.dahiya@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/* arch/arm/plat-s5p/irq.c
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P - Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware/vic.h>
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#include <linux/serial_core.h>
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#include <mach/map.h>
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#include <plat/regs-timer.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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#include <plat/irq-vic-timer.h>
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#include <plat/irq-uart.h>
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/*
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* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static struct s3c_uart_irq uart_irqs[] = {
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[0] = {
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.regs = S5P_VA_UART0,
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.base_irq = IRQ_S5P_UART_BASE0,
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.parent_irq = IRQ_UART0,
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},
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[1] = {
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.regs = S5P_VA_UART1,
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.base_irq = IRQ_S5P_UART_BASE1,
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.parent_irq = IRQ_UART1,
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},
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[2] = {
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.regs = S5P_VA_UART2,
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.base_irq = IRQ_S5P_UART_BASE2,
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.parent_irq = IRQ_UART2,
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},
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#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
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[3] = {
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.regs = S5P_VA_UART3,
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.base_irq = IRQ_S5P_UART_BASE3,
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.parent_irq = IRQ_UART3,
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},
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#endif
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};
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void __init s5p_init_irq(u32 *vic, u32 num_vic)
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{
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int irq;
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/* initialize the VICs */
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for (irq = 0; irq < num_vic; irq++)
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vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
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s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
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s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
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s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
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s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
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s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
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s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
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}
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