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ef04070692
This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Analog Devices Generic AXI ADC IP core driver/library
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* Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
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*
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* Copyright 2012-2020 Analog Devices Inc.
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*/
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#ifndef __ADI_AXI_ADC_H__
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#define __ADI_AXI_ADC_H__
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struct device;
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struct iio_chan_spec;
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/**
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* struct adi_axi_adc_chip_info - Chip specific information
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* @name Chip name
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* @id Chip ID (usually product ID)
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* @channels Channel specifications of type @struct axi_adc_chan_spec
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* @num_channels Number of @channels
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* @scale_table Supported scales by the chip; tuples of 2 ints
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* @num_scales Number of scales in the table
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* @max_rate Maximum sampling rate supported by the device
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*/
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struct adi_axi_adc_chip_info {
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const char *name;
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unsigned int id;
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const struct iio_chan_spec *channels;
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unsigned int num_channels;
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const unsigned int (*scale_table)[2];
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int num_scales;
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unsigned long max_rate;
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};
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/**
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* struct adi_axi_adc_conv - data of the ADC attached to the AXI ADC
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* @chip_info chip info details for the client ADC
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* @preenable_setup op to run in the client before enabling the AXI ADC
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* @reg_access IIO debugfs_reg_access hook for the client ADC
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* @read_raw IIO read_raw hook for the client ADC
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* @write_raw IIO write_raw hook for the client ADC
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*/
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struct adi_axi_adc_conv {
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const struct adi_axi_adc_chip_info *chip_info;
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int (*preenable_setup)(struct adi_axi_adc_conv *conv);
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int (*reg_access)(struct adi_axi_adc_conv *conv, unsigned int reg,
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unsigned int writeval, unsigned int *readval);
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int (*read_raw)(struct adi_axi_adc_conv *conv,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask);
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int (*write_raw)(struct adi_axi_adc_conv *conv,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask);
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};
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struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
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size_t sizeof_priv);
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void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv);
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#endif
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