mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:26:42 +07:00
fbc450b137
Hmm so actually my original patch including this bit was correct, "list = list->next;" confused me :) - will send patch correcting that in a few. Signed-off-by: Jiri Pirko <jpirko@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1169 lines
30 KiB
C
1169 lines
30 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Cavium Networks
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*/
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#include <linux/capability.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/if_vlan.h>
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#include <linux/phy.h>
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#include <linux/spinlock.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-mixx-defs.h>
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#include <asm/octeon/cvmx-agl-defs.h>
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#define DRV_NAME "octeon_mgmt"
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#define DRV_VERSION "2.0"
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#define DRV_DESCRIPTION \
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"Cavium Networks Octeon MII (management) port Network Driver"
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#define OCTEON_MGMT_NAPI_WEIGHT 16
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/*
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* Ring sizes that are powers of two allow for more efficient modulo
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* opertions.
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*/
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#define OCTEON_MGMT_RX_RING_SIZE 512
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#define OCTEON_MGMT_TX_RING_SIZE 128
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/* Allow 8 bytes for vlan and FCS. */
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#define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
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union mgmt_port_ring_entry {
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u64 d64;
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struct {
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u64 reserved_62_63:2;
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/* Length of the buffer/packet in bytes */
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u64 len:14;
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/* For TX, signals that the packet should be timestamped */
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u64 tstamp:1;
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/* The RX error code */
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u64 code:7;
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#define RING_ENTRY_CODE_DONE 0xf
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#define RING_ENTRY_CODE_MORE 0x10
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/* Physical address of the buffer */
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u64 addr:40;
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} s;
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};
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struct octeon_mgmt {
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struct net_device *netdev;
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int port;
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int irq;
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u64 *tx_ring;
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dma_addr_t tx_ring_handle;
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unsigned int tx_next;
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unsigned int tx_next_clean;
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unsigned int tx_current_fill;
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/* The tx_list lock also protects the ring related variables */
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struct sk_buff_head tx_list;
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/* RX variables only touched in napi_poll. No locking necessary. */
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u64 *rx_ring;
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dma_addr_t rx_ring_handle;
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unsigned int rx_next;
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unsigned int rx_next_fill;
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unsigned int rx_current_fill;
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struct sk_buff_head rx_list;
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spinlock_t lock;
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unsigned int last_duplex;
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unsigned int last_link;
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struct device *dev;
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struct napi_struct napi;
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struct tasklet_struct tx_clean_tasklet;
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struct phy_device *phydev;
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};
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static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
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{
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int port = p->port;
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union cvmx_mixx_intena mix_intena;
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
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mix_intena.s.ithena = enable ? 1 : 0;
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cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
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{
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int port = p->port;
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union cvmx_mixx_intena mix_intena;
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port));
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mix_intena.s.othena = enable ? 1 : 0;
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cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p)
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{
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octeon_mgmt_set_rx_irq(p, 1);
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}
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static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p)
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{
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octeon_mgmt_set_rx_irq(p, 0);
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}
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static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p)
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{
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octeon_mgmt_set_tx_irq(p, 1);
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}
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static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p)
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{
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octeon_mgmt_set_tx_irq(p, 0);
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}
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static unsigned int ring_max_fill(unsigned int ring_size)
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{
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return ring_size - 8;
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}
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static unsigned int ring_size_to_bytes(unsigned int ring_size)
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{
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return ring_size * sizeof(union mgmt_port_ring_entry);
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}
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static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
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{
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struct octeon_mgmt *p = netdev_priv(netdev);
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int port = p->port;
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while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
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unsigned int size;
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union mgmt_port_ring_entry re;
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struct sk_buff *skb;
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/* CN56XX pass 1 needs 8 bytes of padding. */
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size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN;
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skb = netdev_alloc_skb(netdev, size);
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if (!skb)
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break;
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skb_reserve(skb, NET_IP_ALIGN);
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__skb_queue_tail(&p->rx_list, skb);
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re.d64 = 0;
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re.s.len = size;
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re.s.addr = dma_map_single(p->dev, skb->data,
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size,
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DMA_FROM_DEVICE);
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/* Put it in the ring. */
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p->rx_ring[p->rx_next_fill] = re.d64;
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dma_sync_single_for_device(p->dev, p->rx_ring_handle,
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ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
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DMA_BIDIRECTIONAL);
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p->rx_next_fill =
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(p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
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p->rx_current_fill++;
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/* Ring the bell. */
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cvmx_write_csr(CVMX_MIXX_IRING2(port), 1);
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}
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}
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static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
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{
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int port = p->port;
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union cvmx_mixx_orcnt mix_orcnt;
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union mgmt_port_ring_entry re;
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struct sk_buff *skb;
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int cleaned = 0;
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unsigned long flags;
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mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
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while (mix_orcnt.s.orcnt) {
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dma_sync_single_for_cpu(p->dev, p->tx_ring_handle,
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ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
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DMA_BIDIRECTIONAL);
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spin_lock_irqsave(&p->tx_list.lock, flags);
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re.d64 = p->tx_ring[p->tx_next_clean];
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p->tx_next_clean =
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(p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE;
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skb = __skb_dequeue(&p->tx_list);
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mix_orcnt.u64 = 0;
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mix_orcnt.s.orcnt = 1;
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/* Acknowledge to hardware that we have the buffer. */
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cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64);
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p->tx_current_fill--;
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spin_unlock_irqrestore(&p->tx_list.lock, flags);
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dma_unmap_single(p->dev, re.s.addr, re.s.len,
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DMA_TO_DEVICE);
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dev_kfree_skb_any(skb);
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cleaned++;
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mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port));
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}
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if (cleaned && netif_queue_stopped(p->netdev))
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netif_wake_queue(p->netdev);
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}
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static void octeon_mgmt_clean_tx_tasklet(unsigned long arg)
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{
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struct octeon_mgmt *p = (struct octeon_mgmt *)arg;
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octeon_mgmt_clean_tx_buffers(p);
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octeon_mgmt_enable_tx_irq(p);
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}
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static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
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{
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struct octeon_mgmt *p = netdev_priv(netdev);
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int port = p->port;
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unsigned long flags;
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u64 drop, bad;
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/* These reads also clear the count registers. */
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drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port));
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bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port));
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if (drop || bad) {
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/* Do an atomic update. */
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spin_lock_irqsave(&p->lock, flags);
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netdev->stats.rx_errors += bad;
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netdev->stats.rx_dropped += drop;
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spin_unlock_irqrestore(&p->lock, flags);
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}
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}
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static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
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{
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struct octeon_mgmt *p = netdev_priv(netdev);
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int port = p->port;
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unsigned long flags;
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union cvmx_agl_gmx_txx_stat0 s0;
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union cvmx_agl_gmx_txx_stat1 s1;
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/* These reads also clear the count registers. */
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s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port));
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s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port));
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if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
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/* Do an atomic update. */
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spin_lock_irqsave(&p->lock, flags);
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netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol;
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netdev->stats.collisions += s1.s.scol + s1.s.mcol;
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spin_unlock_irqrestore(&p->lock, flags);
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}
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}
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/*
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* Dequeue a receive skb and its corresponding ring entry. The ring
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* entry is returned, *pskb is updated to point to the skb.
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*/
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static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
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struct sk_buff **pskb)
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{
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union mgmt_port_ring_entry re;
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dma_sync_single_for_cpu(p->dev, p->rx_ring_handle,
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ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
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DMA_BIDIRECTIONAL);
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re.d64 = p->rx_ring[p->rx_next];
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p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE;
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p->rx_current_fill--;
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*pskb = __skb_dequeue(&p->rx_list);
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dma_unmap_single(p->dev, re.s.addr,
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ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM,
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DMA_FROM_DEVICE);
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return re.d64;
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}
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static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
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{
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int port = p->port;
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struct net_device *netdev = p->netdev;
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union cvmx_mixx_ircnt mix_ircnt;
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union mgmt_port_ring_entry re;
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struct sk_buff *skb;
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struct sk_buff *skb2;
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struct sk_buff *skb_new;
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union mgmt_port_ring_entry re2;
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int rc = 1;
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re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb);
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if (likely(re.s.code == RING_ENTRY_CODE_DONE)) {
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/* A good packet, send it up. */
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skb_put(skb, re.s.len);
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good:
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skb->protocol = eth_type_trans(skb, netdev);
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netdev->stats.rx_packets++;
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netdev->stats.rx_bytes += skb->len;
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netdev->last_rx = jiffies;
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netif_receive_skb(skb);
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rc = 0;
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} else if (re.s.code == RING_ENTRY_CODE_MORE) {
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/*
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* Packet split across skbs. This can happen if we
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* increase the MTU. Buffers that are already in the
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* rx ring can then end up being too small. As the rx
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* ring is refilled, buffers sized for the new MTU
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* will be used and we should go back to the normal
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* non-split case.
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*/
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skb_put(skb, re.s.len);
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do {
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re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
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if (re2.s.code != RING_ENTRY_CODE_MORE
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&& re2.s.code != RING_ENTRY_CODE_DONE)
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goto split_error;
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skb_put(skb2, re2.s.len);
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skb_new = skb_copy_expand(skb, 0, skb2->len,
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GFP_ATOMIC);
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if (!skb_new)
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goto split_error;
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if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new),
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skb2->len))
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goto split_error;
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skb_put(skb_new, skb2->len);
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dev_kfree_skb_any(skb);
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dev_kfree_skb_any(skb2);
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skb = skb_new;
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} while (re2.s.code == RING_ENTRY_CODE_MORE);
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goto good;
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} else {
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/* Some other error, discard it. */
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dev_kfree_skb_any(skb);
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/*
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* Error statistics are accumulated in
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* octeon_mgmt_update_rx_stats.
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*/
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}
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goto done;
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split_error:
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/* Discard the whole mess. */
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dev_kfree_skb_any(skb);
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dev_kfree_skb_any(skb2);
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while (re2.s.code == RING_ENTRY_CODE_MORE) {
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re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
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dev_kfree_skb_any(skb2);
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}
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netdev->stats.rx_errors++;
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done:
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/* Tell the hardware we processed a packet. */
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mix_ircnt.u64 = 0;
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mix_ircnt.s.ircnt = 1;
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cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64);
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return rc;
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}
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static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
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{
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int port = p->port;
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unsigned int work_done = 0;
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union cvmx_mixx_ircnt mix_ircnt;
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int rc;
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mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
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while (work_done < budget && mix_ircnt.s.ircnt) {
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rc = octeon_mgmt_receive_one(p);
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if (!rc)
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work_done++;
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/* Check for more packets. */
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mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port));
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}
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octeon_mgmt_rx_fill_ring(p->netdev);
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return work_done;
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}
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static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget)
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{
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struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi);
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struct net_device *netdev = p->netdev;
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unsigned int work_done = 0;
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work_done = octeon_mgmt_receive_packets(p, budget);
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if (work_done < budget) {
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/* We stopped because no more packets were available. */
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napi_complete(napi);
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octeon_mgmt_enable_rx_irq(p);
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}
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octeon_mgmt_update_rx_stats(netdev);
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return work_done;
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}
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/* Reset the hardware to clean state. */
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static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
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{
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union cvmx_mixx_ctl mix_ctl;
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union cvmx_mixx_bist mix_bist;
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union cvmx_agl_gmx_bist agl_gmx_bist;
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mix_ctl.u64 = 0;
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cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
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do {
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mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port));
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} while (mix_ctl.s.busy);
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mix_ctl.s.reset = 1;
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cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64);
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cvmx_read_csr(CVMX_MIXX_CTL(p->port));
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cvmx_wait(64);
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mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port));
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if (mix_bist.u64)
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dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
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(unsigned long long)mix_bist.u64);
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agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
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if (agl_gmx_bist.u64)
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dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n",
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(unsigned long long)agl_gmx_bist.u64);
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}
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struct octeon_mgmt_cam_state {
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u64 cam[6];
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u64 cam_mask;
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int cam_index;
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};
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|
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static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
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unsigned char *addr)
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{
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int i;
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for (i = 0; i < 6; i++)
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cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));
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|
cs->cam_mask |= (1ULL << cs->cam_index);
|
|
cs->cam_index++;
|
|
}
|
|
|
|
static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
int port = p->port;
|
|
union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
|
|
union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
|
|
unsigned long flags;
|
|
unsigned int prev_packet_enable;
|
|
unsigned int cam_mode = 1; /* 1 - Accept on CAM match */
|
|
unsigned int multicast_mode = 1; /* 1 - Reject all multicast. */
|
|
struct octeon_mgmt_cam_state cam_state;
|
|
struct dev_addr_list *list;
|
|
struct list_head *pos;
|
|
int available_cam_entries;
|
|
|
|
memset(&cam_state, 0, sizeof(cam_state));
|
|
|
|
if ((netdev->flags & IFF_PROMISC) || netdev->dev_addrs.count > 7) {
|
|
cam_mode = 0;
|
|
available_cam_entries = 8;
|
|
} else {
|
|
/*
|
|
* One CAM entry for the primary address, leaves seven
|
|
* for the secondary addresses.
|
|
*/
|
|
available_cam_entries = 7 - netdev->dev_addrs.count;
|
|
}
|
|
|
|
if (netdev->flags & IFF_MULTICAST) {
|
|
if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI) ||
|
|
netdev_mc_count(netdev) > available_cam_entries)
|
|
multicast_mode = 2; /* 1 - Accept all multicast. */
|
|
else
|
|
multicast_mode = 0; /* 0 - Use CAM. */
|
|
}
|
|
|
|
if (cam_mode == 1) {
|
|
/* Add primary address. */
|
|
octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr);
|
|
list_for_each(pos, &netdev->dev_addrs.list) {
|
|
struct netdev_hw_addr *hw_addr;
|
|
hw_addr = list_entry(pos, struct netdev_hw_addr, list);
|
|
octeon_mgmt_cam_state_add(&cam_state, hw_addr->addr);
|
|
list = list->next;
|
|
}
|
|
}
|
|
if (multicast_mode == 0) {
|
|
netdev_for_each_mc_addr(list, netdev)
|
|
octeon_mgmt_cam_state_add(&cam_state, list->da_addr);
|
|
}
|
|
|
|
|
|
spin_lock_irqsave(&p->lock, flags);
|
|
|
|
/* Disable packet I/O. */
|
|
agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
|
|
prev_packet_enable = agl_gmx_prtx.s.en;
|
|
agl_gmx_prtx.s.en = 0;
|
|
cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
|
|
|
|
|
|
adr_ctl.u64 = 0;
|
|
adr_ctl.s.cam_mode = cam_mode;
|
|
adr_ctl.s.mcst = multicast_mode;
|
|
adr_ctl.s.bcst = 1; /* Allow broadcast */
|
|
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64);
|
|
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask);
|
|
|
|
/* Restore packet I/O. */
|
|
agl_gmx_prtx.s.en = prev_packet_enable;
|
|
cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
|
|
|
|
spin_unlock_irqrestore(&p->lock, flags);
|
|
}
|
|
|
|
static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
|
|
{
|
|
struct sockaddr *sa = addr;
|
|
|
|
if (!is_valid_ether_addr(sa->sa_data))
|
|
return -EADDRNOTAVAIL;
|
|
|
|
memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
|
|
|
|
octeon_mgmt_set_rx_filtering(netdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
int port = p->port;
|
|
int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM;
|
|
|
|
/*
|
|
* Limit the MTU to make sure the ethernet packets are between
|
|
* 64 bytes and 16383 bytes.
|
|
*/
|
|
if (size_without_fcs < 64 || size_without_fcs > 16383) {
|
|
dev_warn(p->dev, "MTU must be between %d and %d.\n",
|
|
64 - OCTEON_MGMT_RX_HEADROOM,
|
|
16383 - OCTEON_MGMT_RX_HEADROOM);
|
|
return -EINVAL;
|
|
}
|
|
|
|
netdev->mtu = new_mtu;
|
|
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port),
|
|
(size_without_fcs + 7) & 0xfff8);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
|
|
{
|
|
struct net_device *netdev = dev_id;
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
int port = p->port;
|
|
union cvmx_mixx_isr mixx_isr;
|
|
|
|
mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port));
|
|
|
|
/* Clear any pending interrupts */
|
|
cvmx_write_csr(CVMX_MIXX_ISR(port),
|
|
cvmx_read_csr(CVMX_MIXX_ISR(port)));
|
|
cvmx_read_csr(CVMX_MIXX_ISR(port));
|
|
|
|
if (mixx_isr.s.irthresh) {
|
|
octeon_mgmt_disable_rx_irq(p);
|
|
napi_schedule(&p->napi);
|
|
}
|
|
if (mixx_isr.s.orthresh) {
|
|
octeon_mgmt_disable_tx_irq(p);
|
|
tasklet_schedule(&p->tx_clean_tasklet);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int octeon_mgmt_ioctl(struct net_device *netdev,
|
|
struct ifreq *rq, int cmd)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
|
|
if (!netif_running(netdev))
|
|
return -EINVAL;
|
|
|
|
if (!p->phydev)
|
|
return -EINVAL;
|
|
|
|
return phy_mii_ioctl(p->phydev, if_mii(rq), cmd);
|
|
}
|
|
|
|
static void octeon_mgmt_adjust_link(struct net_device *netdev)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
int port = p->port;
|
|
union cvmx_agl_gmx_prtx_cfg prtx_cfg;
|
|
unsigned long flags;
|
|
int link_changed = 0;
|
|
|
|
spin_lock_irqsave(&p->lock, flags);
|
|
if (p->phydev->link) {
|
|
if (!p->last_link)
|
|
link_changed = 1;
|
|
if (p->last_duplex != p->phydev->duplex) {
|
|
p->last_duplex = p->phydev->duplex;
|
|
prtx_cfg.u64 =
|
|
cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
|
|
prtx_cfg.s.duplex = p->phydev->duplex;
|
|
cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port),
|
|
prtx_cfg.u64);
|
|
}
|
|
} else {
|
|
if (p->last_link)
|
|
link_changed = -1;
|
|
}
|
|
p->last_link = p->phydev->link;
|
|
spin_unlock_irqrestore(&p->lock, flags);
|
|
|
|
if (link_changed != 0) {
|
|
if (link_changed > 0) {
|
|
netif_carrier_on(netdev);
|
|
pr_info("%s: Link is up - %d/%s\n", netdev->name,
|
|
p->phydev->speed,
|
|
DUPLEX_FULL == p->phydev->duplex ?
|
|
"Full" : "Half");
|
|
} else {
|
|
netif_carrier_off(netdev);
|
|
pr_info("%s: Link is down\n", netdev->name);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int octeon_mgmt_init_phy(struct net_device *netdev)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
char phy_id[20];
|
|
|
|
if (octeon_is_simulation()) {
|
|
/* No PHYs in the simulator. */
|
|
netif_carrier_on(netdev);
|
|
return 0;
|
|
}
|
|
|
|
snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port);
|
|
|
|
p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0,
|
|
PHY_INTERFACE_MODE_MII);
|
|
|
|
if (IS_ERR(p->phydev)) {
|
|
p->phydev = NULL;
|
|
return -1;
|
|
}
|
|
|
|
phy_start_aneg(p->phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_mgmt_open(struct net_device *netdev)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
int port = p->port;
|
|
union cvmx_mixx_ctl mix_ctl;
|
|
union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
|
|
union cvmx_mixx_oring1 oring1;
|
|
union cvmx_mixx_iring1 iring1;
|
|
union cvmx_agl_gmx_prtx_cfg prtx_cfg;
|
|
union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
|
|
union cvmx_mixx_irhwm mix_irhwm;
|
|
union cvmx_mixx_orhwm mix_orhwm;
|
|
union cvmx_mixx_intena mix_intena;
|
|
struct sockaddr sa;
|
|
|
|
/* Allocate ring buffers. */
|
|
p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
|
|
GFP_KERNEL);
|
|
if (!p->tx_ring)
|
|
return -ENOMEM;
|
|
p->tx_ring_handle =
|
|
dma_map_single(p->dev, p->tx_ring,
|
|
ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
|
|
DMA_BIDIRECTIONAL);
|
|
p->tx_next = 0;
|
|
p->tx_next_clean = 0;
|
|
p->tx_current_fill = 0;
|
|
|
|
|
|
p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
|
|
GFP_KERNEL);
|
|
if (!p->rx_ring)
|
|
goto err_nomem;
|
|
p->rx_ring_handle =
|
|
dma_map_single(p->dev, p->rx_ring,
|
|
ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
p->rx_next = 0;
|
|
p->rx_next_fill = 0;
|
|
p->rx_current_fill = 0;
|
|
|
|
octeon_mgmt_reset_hw(p);
|
|
|
|
mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
|
|
|
|
/* Bring it out of reset if needed. */
|
|
if (mix_ctl.s.reset) {
|
|
mix_ctl.s.reset = 0;
|
|
cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
|
|
do {
|
|
mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port));
|
|
} while (mix_ctl.s.reset);
|
|
}
|
|
|
|
agl_gmx_inf_mode.u64 = 0;
|
|
agl_gmx_inf_mode.s.en = 1;
|
|
cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
|
|
|
|
oring1.u64 = 0;
|
|
oring1.s.obase = p->tx_ring_handle >> 3;
|
|
oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
|
|
cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64);
|
|
|
|
iring1.u64 = 0;
|
|
iring1.s.ibase = p->rx_ring_handle >> 3;
|
|
iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
|
|
cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64);
|
|
|
|
/* Disable packet I/O. */
|
|
prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
|
|
prtx_cfg.s.en = 0;
|
|
cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
|
|
|
|
memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
|
|
octeon_mgmt_set_mac_address(netdev, &sa);
|
|
|
|
octeon_mgmt_change_mtu(netdev, netdev->mtu);
|
|
|
|
/*
|
|
* Enable the port HW. Packets are not allowed until
|
|
* cvmx_mgmt_port_enable() is called.
|
|
*/
|
|
mix_ctl.u64 = 0;
|
|
mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */
|
|
mix_ctl.s.en = 1; /* Enable the port */
|
|
mix_ctl.s.nbtarb = 0; /* Arbitration mode */
|
|
/* MII CB-request FIFO programmable high watermark */
|
|
mix_ctl.s.mrq_hwm = 1;
|
|
cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64);
|
|
|
|
if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
|
|
|| OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
|
|
/*
|
|
* Force compensation values, as they are not
|
|
* determined properly by HW
|
|
*/
|
|
union cvmx_agl_gmx_drv_ctl drv_ctl;
|
|
|
|
drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
|
|
if (port) {
|
|
drv_ctl.s.byp_en1 = 1;
|
|
drv_ctl.s.nctl1 = 6;
|
|
drv_ctl.s.pctl1 = 6;
|
|
} else {
|
|
drv_ctl.s.byp_en = 1;
|
|
drv_ctl.s.nctl = 6;
|
|
drv_ctl.s.pctl = 6;
|
|
}
|
|
cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
|
|
}
|
|
|
|
octeon_mgmt_rx_fill_ring(netdev);
|
|
|
|
/* Clear statistics. */
|
|
/* Clear on read. */
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0);
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0);
|
|
|
|
cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1);
|
|
cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0);
|
|
cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0);
|
|
|
|
/* Clear any pending interrupts */
|
|
cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port)));
|
|
|
|
if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
|
|
netdev)) {
|
|
dev_err(p->dev, "request_irq(%d) failed.\n", p->irq);
|
|
goto err_noirq;
|
|
}
|
|
|
|
/* Interrupt every single RX packet */
|
|
mix_irhwm.u64 = 0;
|
|
mix_irhwm.s.irhwm = 0;
|
|
cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64);
|
|
|
|
/* Interrupt when we have 5 or more packets to clean. */
|
|
mix_orhwm.u64 = 0;
|
|
mix_orhwm.s.orhwm = 5;
|
|
cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64);
|
|
|
|
/* Enable receive and transmit interrupts */
|
|
mix_intena.u64 = 0;
|
|
mix_intena.s.ithena = 1;
|
|
mix_intena.s.othena = 1;
|
|
cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64);
|
|
|
|
|
|
/* Enable packet I/O. */
|
|
|
|
rxx_frm_ctl.u64 = 0;
|
|
rxx_frm_ctl.s.pre_align = 1;
|
|
/*
|
|
* When set, disables the length check for non-min sized pkts
|
|
* with padding in the client data.
|
|
*/
|
|
rxx_frm_ctl.s.pad_len = 1;
|
|
/* When set, disables the length check for VLAN pkts */
|
|
rxx_frm_ctl.s.vlan_len = 1;
|
|
/* When set, PREAMBLE checking is less strict */
|
|
rxx_frm_ctl.s.pre_free = 1;
|
|
/* Control Pause Frames can match station SMAC */
|
|
rxx_frm_ctl.s.ctl_smac = 0;
|
|
/* Control Pause Frames can match globally assign Multicast address */
|
|
rxx_frm_ctl.s.ctl_mcst = 1;
|
|
/* Forward pause information to TX block */
|
|
rxx_frm_ctl.s.ctl_bck = 1;
|
|
/* Drop Control Pause Frames */
|
|
rxx_frm_ctl.s.ctl_drp = 1;
|
|
/* Strip off the preamble */
|
|
rxx_frm_ctl.s.pre_strp = 1;
|
|
/*
|
|
* This port is configured to send PREAMBLE+SFD to begin every
|
|
* frame. GMX checks that the PREAMBLE is sent correctly.
|
|
*/
|
|
rxx_frm_ctl.s.pre_chk = 1;
|
|
cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
|
|
|
|
/* Enable the AGL block */
|
|
agl_gmx_inf_mode.u64 = 0;
|
|
agl_gmx_inf_mode.s.en = 1;
|
|
cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
|
|
|
|
/* Configure the port duplex and enables */
|
|
prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
|
|
prtx_cfg.s.tx_en = 1;
|
|
prtx_cfg.s.rx_en = 1;
|
|
prtx_cfg.s.en = 1;
|
|
p->last_duplex = 1;
|
|
prtx_cfg.s.duplex = p->last_duplex;
|
|
cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64);
|
|
|
|
p->last_link = 0;
|
|
netif_carrier_off(netdev);
|
|
|
|
if (octeon_mgmt_init_phy(netdev)) {
|
|
dev_err(p->dev, "Cannot initialize PHY.\n");
|
|
goto err_noirq;
|
|
}
|
|
|
|
netif_wake_queue(netdev);
|
|
napi_enable(&p->napi);
|
|
|
|
return 0;
|
|
err_noirq:
|
|
octeon_mgmt_reset_hw(p);
|
|
dma_unmap_single(p->dev, p->rx_ring_handle,
|
|
ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
|
|
DMA_BIDIRECTIONAL);
|
|
kfree(p->rx_ring);
|
|
err_nomem:
|
|
dma_unmap_single(p->dev, p->tx_ring_handle,
|
|
ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
|
|
DMA_BIDIRECTIONAL);
|
|
kfree(p->tx_ring);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static int octeon_mgmt_stop(struct net_device *netdev)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
|
|
napi_disable(&p->napi);
|
|
netif_stop_queue(netdev);
|
|
|
|
if (p->phydev)
|
|
phy_disconnect(p->phydev);
|
|
|
|
netif_carrier_off(netdev);
|
|
|
|
octeon_mgmt_reset_hw(p);
|
|
|
|
|
|
free_irq(p->irq, netdev);
|
|
|
|
/* dma_unmap is a nop on Octeon, so just free everything. */
|
|
skb_queue_purge(&p->tx_list);
|
|
skb_queue_purge(&p->rx_list);
|
|
|
|
dma_unmap_single(p->dev, p->rx_ring_handle,
|
|
ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
|
|
DMA_BIDIRECTIONAL);
|
|
kfree(p->rx_ring);
|
|
|
|
dma_unmap_single(p->dev, p->tx_ring_handle,
|
|
ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
|
|
DMA_BIDIRECTIONAL);
|
|
kfree(p->tx_ring);
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
int port = p->port;
|
|
union mgmt_port_ring_entry re;
|
|
unsigned long flags;
|
|
|
|
re.d64 = 0;
|
|
re.s.len = skb->len;
|
|
re.s.addr = dma_map_single(p->dev, skb->data,
|
|
skb->len,
|
|
DMA_TO_DEVICE);
|
|
|
|
spin_lock_irqsave(&p->tx_list.lock, flags);
|
|
|
|
if (unlikely(p->tx_current_fill >=
|
|
ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) {
|
|
spin_unlock_irqrestore(&p->tx_list.lock, flags);
|
|
|
|
dma_unmap_single(p->dev, re.s.addr, re.s.len,
|
|
DMA_TO_DEVICE);
|
|
|
|
netif_stop_queue(netdev);
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
|
|
__skb_queue_tail(&p->tx_list, skb);
|
|
|
|
/* Put it in the ring. */
|
|
p->tx_ring[p->tx_next] = re.d64;
|
|
p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE;
|
|
p->tx_current_fill++;
|
|
|
|
spin_unlock_irqrestore(&p->tx_list.lock, flags);
|
|
|
|
dma_sync_single_for_device(p->dev, p->tx_ring_handle,
|
|
ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
netdev->stats.tx_packets++;
|
|
netdev->stats.tx_bytes += skb->len;
|
|
|
|
/* Ring the bell. */
|
|
cvmx_write_csr(CVMX_MIXX_ORING2(port), 1);
|
|
|
|
netdev->trans_start = jiffies;
|
|
octeon_mgmt_clean_tx_buffers(p);
|
|
octeon_mgmt_update_tx_stats(netdev);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
static void octeon_mgmt_poll_controller(struct net_device *netdev)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
|
|
octeon_mgmt_receive_packets(p, 16);
|
|
octeon_mgmt_update_rx_stats(netdev);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
static void octeon_mgmt_get_drvinfo(struct net_device *netdev,
|
|
struct ethtool_drvinfo *info)
|
|
{
|
|
strncpy(info->driver, DRV_NAME, sizeof(info->driver));
|
|
strncpy(info->version, DRV_VERSION, sizeof(info->version));
|
|
strncpy(info->fw_version, "N/A", sizeof(info->fw_version));
|
|
strncpy(info->bus_info, "N/A", sizeof(info->bus_info));
|
|
info->n_stats = 0;
|
|
info->testinfo_len = 0;
|
|
info->regdump_len = 0;
|
|
info->eedump_len = 0;
|
|
}
|
|
|
|
static int octeon_mgmt_get_settings(struct net_device *netdev,
|
|
struct ethtool_cmd *cmd)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
|
|
if (p->phydev)
|
|
return phy_ethtool_gset(p->phydev, cmd);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int octeon_mgmt_set_settings(struct net_device *netdev,
|
|
struct ethtool_cmd *cmd)
|
|
{
|
|
struct octeon_mgmt *p = netdev_priv(netdev);
|
|
|
|
if (!capable(CAP_NET_ADMIN))
|
|
return -EPERM;
|
|
|
|
if (p->phydev)
|
|
return phy_ethtool_sset(p->phydev, cmd);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct ethtool_ops octeon_mgmt_ethtool_ops = {
|
|
.get_drvinfo = octeon_mgmt_get_drvinfo,
|
|
.get_link = ethtool_op_get_link,
|
|
.get_settings = octeon_mgmt_get_settings,
|
|
.set_settings = octeon_mgmt_set_settings
|
|
};
|
|
|
|
static const struct net_device_ops octeon_mgmt_ops = {
|
|
.ndo_open = octeon_mgmt_open,
|
|
.ndo_stop = octeon_mgmt_stop,
|
|
.ndo_start_xmit = octeon_mgmt_xmit,
|
|
.ndo_set_rx_mode = octeon_mgmt_set_rx_filtering,
|
|
.ndo_set_multicast_list = octeon_mgmt_set_rx_filtering,
|
|
.ndo_set_mac_address = octeon_mgmt_set_mac_address,
|
|
.ndo_do_ioctl = octeon_mgmt_ioctl,
|
|
.ndo_change_mtu = octeon_mgmt_change_mtu,
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = octeon_mgmt_poll_controller,
|
|
#endif
|
|
};
|
|
|
|
static int __init octeon_mgmt_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res_irq;
|
|
struct net_device *netdev;
|
|
struct octeon_mgmt *p;
|
|
int i;
|
|
|
|
netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
|
|
if (netdev == NULL)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(&pdev->dev, netdev);
|
|
p = netdev_priv(netdev);
|
|
netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll,
|
|
OCTEON_MGMT_NAPI_WEIGHT);
|
|
|
|
p->netdev = netdev;
|
|
p->dev = &pdev->dev;
|
|
|
|
p->port = pdev->id;
|
|
snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
|
|
|
|
res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (!res_irq)
|
|
goto err;
|
|
|
|
p->irq = res_irq->start;
|
|
spin_lock_init(&p->lock);
|
|
|
|
skb_queue_head_init(&p->tx_list);
|
|
skb_queue_head_init(&p->rx_list);
|
|
tasklet_init(&p->tx_clean_tasklet,
|
|
octeon_mgmt_clean_tx_tasklet, (unsigned long)p);
|
|
|
|
netdev->netdev_ops = &octeon_mgmt_ops;
|
|
netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
|
|
|
|
|
|
/* The mgmt ports get the first N MACs. */
|
|
for (i = 0; i < 6; i++)
|
|
netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i];
|
|
netdev->dev_addr[5] += p->port;
|
|
|
|
if (p->port >= octeon_bootinfo->mac_addr_count)
|
|
dev_err(&pdev->dev,
|
|
"Error %s: Using MAC outside of the assigned range: %pM\n",
|
|
netdev->name, netdev->dev_addr);
|
|
|
|
if (register_netdev(netdev))
|
|
goto err;
|
|
|
|
dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
|
|
return 0;
|
|
err:
|
|
free_netdev(netdev);
|
|
return -ENOENT;
|
|
}
|
|
|
|
static int __exit octeon_mgmt_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *netdev = dev_get_drvdata(&pdev->dev);
|
|
|
|
unregister_netdev(netdev);
|
|
free_netdev(netdev);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver octeon_mgmt_driver = {
|
|
.driver = {
|
|
.name = "octeon_mgmt",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = octeon_mgmt_probe,
|
|
.remove = __exit_p(octeon_mgmt_remove),
|
|
};
|
|
|
|
extern void octeon_mdiobus_force_mod_depencency(void);
|
|
|
|
static int __init octeon_mgmt_mod_init(void)
|
|
{
|
|
/* Force our mdiobus driver module to be loaded first. */
|
|
octeon_mdiobus_force_mod_depencency();
|
|
return platform_driver_register(&octeon_mgmt_driver);
|
|
}
|
|
|
|
static void __exit octeon_mgmt_mod_exit(void)
|
|
{
|
|
platform_driver_unregister(&octeon_mgmt_driver);
|
|
}
|
|
|
|
module_init(octeon_mgmt_mod_init);
|
|
module_exit(octeon_mgmt_mod_exit);
|
|
|
|
MODULE_DESCRIPTION(DRV_DESCRIPTION);
|
|
MODULE_AUTHOR("David Daney");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION(DRV_VERSION);
|