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fbb2de891c
PCIe in TI's AM654 devices is by default configured to work in GEN3 mode. However PCIe does not work reliably in GEN3 mode because of SERDES configuration. Add support to set the link speed to GEN1, GEN2 or GEN3 based on "max-link-speed" DT property with GEN2 as the default speed if "max-link-speed" is absent. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
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.. | ||
Kconfig | ||
Makefile | ||
pci-dra7xx.c | ||
pci-exynos.c | ||
pci-imx6.c | ||
pci-keystone.c | ||
pci-layerscape-ep.c | ||
pci-layerscape.c | ||
pci-meson.c | ||
pcie-armada8k.c | ||
pcie-artpec6.c | ||
pcie-designware-ep.c | ||
pcie-designware-host.c | ||
pcie-designware-plat.c | ||
pcie-designware.c | ||
pcie-designware.h | ||
pcie-hisi.c | ||
pcie-histb.c | ||
pcie-kirin.c | ||
pcie-qcom.c | ||
pcie-spear13xx.c | ||
pcie-uniphier.c |