mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 15:16:39 +07:00
921eeadbbd
Using kmem_cache_zalloc() instead of kmem_cache_alloc() and memset(). spatch with a semantic match is used to found this problem. (http://coccinelle.lip6.fr/) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
907 lines
24 KiB
C
907 lines
24 KiB
C
/*
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* Intel I/OAT DMA Linux driver
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* Copyright(c) 2004 - 2009 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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/*
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* This driver supports an Intel I/OAT DMA engine (versions >= 2), which
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* does asynchronous data movement and checksumming operations.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/prefetch.h>
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#include <linux/i7300_idle.h>
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#include "dma.h"
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#include "dma_v2.h"
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#include "registers.h"
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#include "hw.h"
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#include "../dmaengine.h"
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int ioat_ring_alloc_order = 8;
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module_param(ioat_ring_alloc_order, int, 0644);
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MODULE_PARM_DESC(ioat_ring_alloc_order,
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"ioat2+: allocate 2^n descriptors per channel"
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" (default: 8 max: 16)");
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static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
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module_param(ioat_ring_max_alloc_order, int, 0644);
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MODULE_PARM_DESC(ioat_ring_max_alloc_order,
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"ioat2+: upper limit for ring size (default: 16)");
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void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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ioat->dmacount += ioat2_ring_pending(ioat);
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ioat->issued = ioat->head;
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writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
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dev_dbg(to_dev(chan),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
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}
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void ioat2_issue_pending(struct dma_chan *c)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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if (ioat2_ring_pending(ioat)) {
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spin_lock_bh(&ioat->prep_lock);
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__ioat2_issue_pending(ioat);
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spin_unlock_bh(&ioat->prep_lock);
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}
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}
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/**
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* ioat2_update_pending - log pending descriptors
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* @ioat: ioat2+ channel
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*
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* Check if the number of unsubmitted descriptors has exceeded the
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* watermark. Called with prep_lock held
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*/
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static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
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{
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if (ioat2_ring_pending(ioat) > ioat_pending_level)
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__ioat2_issue_pending(ioat);
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}
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static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
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{
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struct ioat_ring_ent *desc;
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struct ioat_dma_descriptor *hw;
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if (ioat2_ring_space(ioat) < 1) {
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dev_err(to_dev(&ioat->base),
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"Unable to start null desc - ring full\n");
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return;
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}
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dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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desc = ioat2_get_ring_ent(ioat, ioat->head);
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hw = desc->hw;
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hw->ctl = 0;
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hw->ctl_f.null = 1;
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hw->ctl_f.int_en = 1;
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hw->ctl_f.compl_write = 1;
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/* set size to non-zero value (channel returns error when size is 0) */
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hw->size = NULL_DESC_BUFFER_SIZE;
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hw->src_addr = 0;
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hw->dst_addr = 0;
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async_tx_ack(&desc->txd);
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ioat2_set_chainaddr(ioat, desc->txd.phys);
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dump_desc_dbg(ioat, desc);
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wmb();
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ioat->head += 1;
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__ioat2_issue_pending(ioat);
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}
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static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
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{
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spin_lock_bh(&ioat->prep_lock);
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__ioat2_start_null_desc(ioat);
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spin_unlock_bh(&ioat->prep_lock);
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}
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static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
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{
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struct ioat_chan_common *chan = &ioat->base;
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struct dma_async_tx_descriptor *tx;
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struct ioat_ring_ent *desc;
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bool seen_current = false;
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u16 active;
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int idx = ioat->tail, i;
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dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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active = ioat2_ring_active(ioat);
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for (i = 0; i < active && !seen_current; i++) {
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smp_read_barrier_depends();
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prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
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desc = ioat2_get_ring_ent(ioat, idx + i);
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tx = &desc->txd;
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dump_desc_dbg(ioat, desc);
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if (tx->cookie) {
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ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
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dma_cookie_complete(tx);
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if (tx->callback) {
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tx->callback(tx->callback_param);
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tx->callback = NULL;
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}
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}
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if (tx->phys == phys_complete)
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seen_current = true;
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}
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smp_mb(); /* finish all descriptor reads before incrementing tail */
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ioat->tail = idx + i;
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BUG_ON(active && !seen_current); /* no active descs have written a completion? */
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chan->last_completion = phys_complete;
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if (active - i == 0) {
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dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
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__func__);
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clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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}
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/**
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* ioat2_cleanup - clean finished descriptors (advance tail pointer)
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* @chan: ioat channel to be cleaned up
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*/
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static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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dma_addr_t phys_complete;
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spin_lock_bh(&chan->cleanup_lock);
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if (ioat_cleanup_preamble(chan, &phys_complete))
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__cleanup(ioat, phys_complete);
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spin_unlock_bh(&chan->cleanup_lock);
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}
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void ioat2_cleanup_event(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
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ioat2_cleanup(ioat);
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writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
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}
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void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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/* set the tail to be re-issued */
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ioat->issued = ioat->tail;
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ioat->dmacount = 0;
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set_bit(IOAT_COMPLETION_PENDING, &chan->state);
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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dev_dbg(to_dev(chan),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
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if (ioat2_ring_pending(ioat)) {
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struct ioat_ring_ent *desc;
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desc = ioat2_get_ring_ent(ioat, ioat->tail);
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ioat2_set_chainaddr(ioat, desc->txd.phys);
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__ioat2_issue_pending(ioat);
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} else
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__ioat2_start_null_desc(ioat);
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}
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int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo)
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{
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unsigned long end = jiffies + tmo;
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int err = 0;
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u32 status;
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status = ioat_chansts(chan);
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if (is_ioat_active(status) || is_ioat_idle(status))
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ioat_suspend(chan);
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while (is_ioat_active(status) || is_ioat_idle(status)) {
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if (tmo && time_after(jiffies, end)) {
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err = -ETIMEDOUT;
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break;
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}
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status = ioat_chansts(chan);
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cpu_relax();
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}
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return err;
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}
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int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo)
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{
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unsigned long end = jiffies + tmo;
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int err = 0;
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ioat_reset(chan);
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while (ioat_reset_pending(chan)) {
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if (end && time_after(jiffies, end)) {
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err = -ETIMEDOUT;
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break;
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}
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cpu_relax();
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}
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return err;
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}
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static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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dma_addr_t phys_complete;
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ioat2_quiesce(chan, 0);
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if (ioat_cleanup_preamble(chan, &phys_complete))
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__cleanup(ioat, phys_complete);
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__ioat2_restart_chan(ioat);
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}
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void ioat2_timer_event(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
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struct ioat_chan_common *chan = &ioat->base;
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if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
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dma_addr_t phys_complete;
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u64 status;
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status = ioat_chansts(chan);
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/* when halted due to errors check for channel
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* programming errors before advancing the completion state
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*/
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if (is_ioat_halted(status)) {
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u32 chanerr;
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
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__func__, chanerr);
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if (test_bit(IOAT_RUN, &chan->state))
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BUG_ON(is_ioat_bug(chanerr));
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else /* we never got off the ground */
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return;
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}
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/* if we haven't made progress and we have already
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* acknowledged a pending completion once, then be more
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* forceful with a restart
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*/
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spin_lock_bh(&chan->cleanup_lock);
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if (ioat_cleanup_preamble(chan, &phys_complete)) {
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__cleanup(ioat, phys_complete);
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} else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
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spin_lock_bh(&ioat->prep_lock);
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ioat2_restart_channel(ioat);
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spin_unlock_bh(&ioat->prep_lock);
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} else {
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set_bit(IOAT_COMPLETION_ACK, &chan->state);
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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}
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spin_unlock_bh(&chan->cleanup_lock);
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} else {
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u16 active;
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/* if the ring is idle, empty, and oversized try to step
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* down the size
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*/
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spin_lock_bh(&chan->cleanup_lock);
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spin_lock_bh(&ioat->prep_lock);
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active = ioat2_ring_active(ioat);
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if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
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reshape_ring(ioat, ioat->alloc_order-1);
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spin_unlock_bh(&ioat->prep_lock);
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spin_unlock_bh(&chan->cleanup_lock);
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/* keep shrinking until we get back to our minimum
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* default size
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*/
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if (ioat->alloc_order > ioat_get_alloc_order())
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mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
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}
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}
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static int ioat2_reset_hw(struct ioat_chan_common *chan)
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{
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/* throw away whatever the channel was doing and get it initialized */
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u32 chanerr;
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ioat2_quiesce(chan, msecs_to_jiffies(100));
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
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return ioat2_reset_sync(chan, msecs_to_jiffies(200));
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}
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/**
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* ioat2_enumerate_channels - find and initialize the device's channels
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* @device: the device to be enumerated
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*/
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int ioat2_enumerate_channels(struct ioatdma_device *device)
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{
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struct ioat2_dma_chan *ioat;
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struct device *dev = &device->pdev->dev;
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struct dma_device *dma = &device->common;
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u8 xfercap_log;
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int i;
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INIT_LIST_HEAD(&dma->channels);
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dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
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dma->chancnt &= 0x1f; /* bits [4:0] valid */
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if (dma->chancnt > ARRAY_SIZE(device->idx)) {
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dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
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dma->chancnt, ARRAY_SIZE(device->idx));
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dma->chancnt = ARRAY_SIZE(device->idx);
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}
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xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
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xfercap_log &= 0x1f; /* bits [4:0] valid */
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if (xfercap_log == 0)
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return 0;
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dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
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/* FIXME which i/oat version is i7300? */
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#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
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if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
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dma->chancnt--;
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#endif
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for (i = 0; i < dma->chancnt; i++) {
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ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
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if (!ioat)
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break;
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ioat_init_channel(device, &ioat->base, i);
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ioat->xfercap_log = xfercap_log;
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spin_lock_init(&ioat->prep_lock);
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if (device->reset_hw(&ioat->base)) {
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i = 0;
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break;
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}
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}
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dma->chancnt = i;
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return i;
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}
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static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
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{
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struct dma_chan *c = tx->chan;
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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struct ioat_chan_common *chan = &ioat->base;
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dma_cookie_t cookie;
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cookie = dma_cookie_assign(tx);
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dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
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if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
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mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
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/* make descriptor updates visible before advancing ioat->head,
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* this is purposefully not smp_wmb() since we are also
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* publishing the descriptor updates to a dma device
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*/
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wmb();
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ioat->head += ioat->produce;
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ioat2_update_pending(ioat);
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spin_unlock_bh(&ioat->prep_lock);
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return cookie;
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}
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static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
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{
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struct ioat_dma_descriptor *hw;
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struct ioat_ring_ent *desc;
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struct ioatdma_device *dma;
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dma_addr_t phys;
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dma = to_ioatdma_device(chan->device);
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hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
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if (!hw)
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return NULL;
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memset(hw, 0, sizeof(*hw));
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desc = kmem_cache_zalloc(ioat2_cache, flags);
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if (!desc) {
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pci_pool_free(dma->dma_pool, hw, phys);
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return NULL;
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}
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dma_async_tx_descriptor_init(&desc->txd, chan);
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desc->txd.tx_submit = ioat2_tx_submit_unlock;
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desc->hw = hw;
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desc->txd.phys = phys;
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return desc;
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}
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static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
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{
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struct ioatdma_device *dma;
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dma = to_ioatdma_device(chan->device);
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pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
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kmem_cache_free(ioat2_cache, desc);
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}
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static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
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{
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struct ioat_ring_ent **ring;
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int descs = 1 << order;
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int i;
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if (order > ioat_get_max_alloc_order())
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return NULL;
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/* allocate the array to hold the software ring */
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ring = kcalloc(descs, sizeof(*ring), flags);
|
|
if (!ring)
|
|
return NULL;
|
|
for (i = 0; i < descs; i++) {
|
|
ring[i] = ioat2_alloc_ring_ent(c, flags);
|
|
if (!ring[i]) {
|
|
while (i--)
|
|
ioat2_free_ring_ent(ring[i], c);
|
|
kfree(ring);
|
|
return NULL;
|
|
}
|
|
set_desc_id(ring[i], i);
|
|
}
|
|
|
|
/* link descs */
|
|
for (i = 0; i < descs-1; i++) {
|
|
struct ioat_ring_ent *next = ring[i+1];
|
|
struct ioat_dma_descriptor *hw = ring[i]->hw;
|
|
|
|
hw->next = next->txd.phys;
|
|
}
|
|
ring[i]->hw->next = ring[0]->txd.phys;
|
|
|
|
return ring;
|
|
}
|
|
|
|
void ioat2_free_chan_resources(struct dma_chan *c);
|
|
|
|
/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
|
|
* @chan: channel to be initialized
|
|
*/
|
|
int ioat2_alloc_chan_resources(struct dma_chan *c)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
struct ioat_chan_common *chan = &ioat->base;
|
|
struct ioat_ring_ent **ring;
|
|
u64 status;
|
|
int order;
|
|
int i = 0;
|
|
|
|
/* have we already been set up? */
|
|
if (ioat->ring)
|
|
return 1 << ioat->alloc_order;
|
|
|
|
/* Setup register to interrupt and write completion status on error */
|
|
writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
|
|
|
|
/* allocate a completion writeback area */
|
|
/* doing 2 32bit writes to mmio since 1 64b write doesn't work */
|
|
chan->completion = pci_pool_alloc(chan->device->completion_pool,
|
|
GFP_KERNEL, &chan->completion_dma);
|
|
if (!chan->completion)
|
|
return -ENOMEM;
|
|
|
|
memset(chan->completion, 0, sizeof(*chan->completion));
|
|
writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
|
|
chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
|
|
writel(((u64) chan->completion_dma) >> 32,
|
|
chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
|
|
|
|
order = ioat_get_alloc_order();
|
|
ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
|
|
if (!ring)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_bh(&chan->cleanup_lock);
|
|
spin_lock_bh(&ioat->prep_lock);
|
|
ioat->ring = ring;
|
|
ioat->head = 0;
|
|
ioat->issued = 0;
|
|
ioat->tail = 0;
|
|
ioat->alloc_order = order;
|
|
spin_unlock_bh(&ioat->prep_lock);
|
|
spin_unlock_bh(&chan->cleanup_lock);
|
|
|
|
tasklet_enable(&chan->cleanup_task);
|
|
ioat2_start_null_desc(ioat);
|
|
|
|
/* check that we got off the ground */
|
|
do {
|
|
udelay(1);
|
|
status = ioat_chansts(chan);
|
|
} while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
|
|
|
|
if (is_ioat_active(status) || is_ioat_idle(status)) {
|
|
set_bit(IOAT_RUN, &chan->state);
|
|
return 1 << ioat->alloc_order;
|
|
} else {
|
|
u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
|
|
|
|
dev_WARN(to_dev(chan),
|
|
"failed to start channel chanerr: %#x\n", chanerr);
|
|
ioat2_free_chan_resources(c);
|
|
return -EFAULT;
|
|
}
|
|
}
|
|
|
|
bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
|
|
{
|
|
/* reshape differs from normal ring allocation in that we want
|
|
* to allocate a new software ring while only
|
|
* extending/truncating the hardware ring
|
|
*/
|
|
struct ioat_chan_common *chan = &ioat->base;
|
|
struct dma_chan *c = &chan->common;
|
|
const u32 curr_size = ioat2_ring_size(ioat);
|
|
const u16 active = ioat2_ring_active(ioat);
|
|
const u32 new_size = 1 << order;
|
|
struct ioat_ring_ent **ring;
|
|
u16 i;
|
|
|
|
if (order > ioat_get_max_alloc_order())
|
|
return false;
|
|
|
|
/* double check that we have at least 1 free descriptor */
|
|
if (active == curr_size)
|
|
return false;
|
|
|
|
/* when shrinking, verify that we can hold the current active
|
|
* set in the new ring
|
|
*/
|
|
if (active >= new_size)
|
|
return false;
|
|
|
|
/* allocate the array to hold the software ring */
|
|
ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
|
|
if (!ring)
|
|
return false;
|
|
|
|
/* allocate/trim descriptors as needed */
|
|
if (new_size > curr_size) {
|
|
/* copy current descriptors to the new ring */
|
|
for (i = 0; i < curr_size; i++) {
|
|
u16 curr_idx = (ioat->tail+i) & (curr_size-1);
|
|
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
|
|
|
ring[new_idx] = ioat->ring[curr_idx];
|
|
set_desc_id(ring[new_idx], new_idx);
|
|
}
|
|
|
|
/* add new descriptors to the ring */
|
|
for (i = curr_size; i < new_size; i++) {
|
|
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
|
|
|
ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
|
|
if (!ring[new_idx]) {
|
|
while (i--) {
|
|
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
|
|
|
ioat2_free_ring_ent(ring[new_idx], c);
|
|
}
|
|
kfree(ring);
|
|
return false;
|
|
}
|
|
set_desc_id(ring[new_idx], new_idx);
|
|
}
|
|
|
|
/* hw link new descriptors */
|
|
for (i = curr_size-1; i < new_size; i++) {
|
|
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
|
struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
|
|
struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
|
|
|
|
hw->next = next->txd.phys;
|
|
}
|
|
} else {
|
|
struct ioat_dma_descriptor *hw;
|
|
struct ioat_ring_ent *next;
|
|
|
|
/* copy current descriptors to the new ring, dropping the
|
|
* removed descriptors
|
|
*/
|
|
for (i = 0; i < new_size; i++) {
|
|
u16 curr_idx = (ioat->tail+i) & (curr_size-1);
|
|
u16 new_idx = (ioat->tail+i) & (new_size-1);
|
|
|
|
ring[new_idx] = ioat->ring[curr_idx];
|
|
set_desc_id(ring[new_idx], new_idx);
|
|
}
|
|
|
|
/* free deleted descriptors */
|
|
for (i = new_size; i < curr_size; i++) {
|
|
struct ioat_ring_ent *ent;
|
|
|
|
ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
|
|
ioat2_free_ring_ent(ent, c);
|
|
}
|
|
|
|
/* fix up hardware ring */
|
|
hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
|
|
next = ring[(ioat->tail+new_size) & (new_size-1)];
|
|
hw->next = next->txd.phys;
|
|
}
|
|
|
|
dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
|
|
__func__, new_size);
|
|
|
|
kfree(ioat->ring);
|
|
ioat->ring = ring;
|
|
ioat->alloc_order = order;
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* ioat2_check_space_lock - verify space and grab ring producer lock
|
|
* @ioat: ioat2,3 channel (ring) to operate on
|
|
* @num_descs: allocation length
|
|
*/
|
|
int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs)
|
|
{
|
|
struct ioat_chan_common *chan = &ioat->base;
|
|
bool retry;
|
|
|
|
retry:
|
|
spin_lock_bh(&ioat->prep_lock);
|
|
/* never allow the last descriptor to be consumed, we need at
|
|
* least one free at all times to allow for on-the-fly ring
|
|
* resizing.
|
|
*/
|
|
if (likely(ioat2_ring_space(ioat) > num_descs)) {
|
|
dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
|
|
__func__, num_descs, ioat->head, ioat->tail, ioat->issued);
|
|
ioat->produce = num_descs;
|
|
return 0; /* with ioat->prep_lock held */
|
|
}
|
|
retry = test_and_set_bit(IOAT_RESHAPE_PENDING, &chan->state);
|
|
spin_unlock_bh(&ioat->prep_lock);
|
|
|
|
/* is another cpu already trying to expand the ring? */
|
|
if (retry)
|
|
goto retry;
|
|
|
|
spin_lock_bh(&chan->cleanup_lock);
|
|
spin_lock_bh(&ioat->prep_lock);
|
|
retry = reshape_ring(ioat, ioat->alloc_order + 1);
|
|
clear_bit(IOAT_RESHAPE_PENDING, &chan->state);
|
|
spin_unlock_bh(&ioat->prep_lock);
|
|
spin_unlock_bh(&chan->cleanup_lock);
|
|
|
|
/* if we were able to expand the ring retry the allocation */
|
|
if (retry)
|
|
goto retry;
|
|
|
|
if (printk_ratelimit())
|
|
dev_dbg(to_dev(chan), "%s: ring full! num_descs: %d (%x:%x:%x)\n",
|
|
__func__, num_descs, ioat->head, ioat->tail, ioat->issued);
|
|
|
|
/* progress reclaim in the allocation failure case we may be
|
|
* called under bh_disabled so we need to trigger the timer
|
|
* event directly
|
|
*/
|
|
if (jiffies > chan->timer.expires && timer_pending(&chan->timer)) {
|
|
struct ioatdma_device *device = chan->device;
|
|
|
|
mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
|
|
device->timer_fn((unsigned long) &chan->common);
|
|
}
|
|
|
|
return -ENOMEM;
|
|
}
|
|
|
|
struct dma_async_tx_descriptor *
|
|
ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
|
|
dma_addr_t dma_src, size_t len, unsigned long flags)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
struct ioat_dma_descriptor *hw;
|
|
struct ioat_ring_ent *desc;
|
|
dma_addr_t dst = dma_dest;
|
|
dma_addr_t src = dma_src;
|
|
size_t total_len = len;
|
|
int num_descs, idx, i;
|
|
|
|
num_descs = ioat2_xferlen_to_descs(ioat, len);
|
|
if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0)
|
|
idx = ioat->head;
|
|
else
|
|
return NULL;
|
|
i = 0;
|
|
do {
|
|
size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
|
|
|
|
desc = ioat2_get_ring_ent(ioat, idx + i);
|
|
hw = desc->hw;
|
|
|
|
hw->size = copy;
|
|
hw->ctl = 0;
|
|
hw->src_addr = src;
|
|
hw->dst_addr = dst;
|
|
|
|
len -= copy;
|
|
dst += copy;
|
|
src += copy;
|
|
dump_desc_dbg(ioat, desc);
|
|
} while (++i < num_descs);
|
|
|
|
desc->txd.flags = flags;
|
|
desc->len = total_len;
|
|
hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
|
|
hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
|
|
hw->ctl_f.compl_write = 1;
|
|
dump_desc_dbg(ioat, desc);
|
|
/* we leave the channel locked to ensure in order submission */
|
|
|
|
return &desc->txd;
|
|
}
|
|
|
|
/**
|
|
* ioat2_free_chan_resources - release all the descriptors
|
|
* @chan: the channel to be cleaned
|
|
*/
|
|
void ioat2_free_chan_resources(struct dma_chan *c)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
struct ioat_chan_common *chan = &ioat->base;
|
|
struct ioatdma_device *device = chan->device;
|
|
struct ioat_ring_ent *desc;
|
|
const u16 total_descs = 1 << ioat->alloc_order;
|
|
int descs;
|
|
int i;
|
|
|
|
/* Before freeing channel resources first check
|
|
* if they have been previously allocated for this channel.
|
|
*/
|
|
if (!ioat->ring)
|
|
return;
|
|
|
|
tasklet_disable(&chan->cleanup_task);
|
|
del_timer_sync(&chan->timer);
|
|
device->cleanup_fn((unsigned long) c);
|
|
device->reset_hw(chan);
|
|
clear_bit(IOAT_RUN, &chan->state);
|
|
|
|
spin_lock_bh(&chan->cleanup_lock);
|
|
spin_lock_bh(&ioat->prep_lock);
|
|
descs = ioat2_ring_space(ioat);
|
|
dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
|
|
for (i = 0; i < descs; i++) {
|
|
desc = ioat2_get_ring_ent(ioat, ioat->head + i);
|
|
ioat2_free_ring_ent(desc, c);
|
|
}
|
|
|
|
if (descs < total_descs)
|
|
dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
|
|
total_descs - descs);
|
|
|
|
for (i = 0; i < total_descs - descs; i++) {
|
|
desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
|
|
dump_desc_dbg(ioat, desc);
|
|
ioat2_free_ring_ent(desc, c);
|
|
}
|
|
|
|
kfree(ioat->ring);
|
|
ioat->ring = NULL;
|
|
ioat->alloc_order = 0;
|
|
pci_pool_free(device->completion_pool, chan->completion,
|
|
chan->completion_dma);
|
|
spin_unlock_bh(&ioat->prep_lock);
|
|
spin_unlock_bh(&chan->cleanup_lock);
|
|
|
|
chan->last_completion = 0;
|
|
chan->completion_dma = 0;
|
|
ioat->dmacount = 0;
|
|
}
|
|
|
|
static ssize_t ring_size_show(struct dma_chan *c, char *page)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
|
|
return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1);
|
|
}
|
|
static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
|
|
|
|
static ssize_t ring_active_show(struct dma_chan *c, char *page)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
|
|
/* ...taken outside the lock, no need to be precise */
|
|
return sprintf(page, "%d\n", ioat2_ring_active(ioat));
|
|
}
|
|
static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
|
|
|
|
static struct attribute *ioat2_attrs[] = {
|
|
&ring_size_attr.attr,
|
|
&ring_active_attr.attr,
|
|
&ioat_cap_attr.attr,
|
|
&ioat_version_attr.attr,
|
|
NULL,
|
|
};
|
|
|
|
struct kobj_type ioat2_ktype = {
|
|
.sysfs_ops = &ioat_sysfs_ops,
|
|
.default_attrs = ioat2_attrs,
|
|
};
|
|
|
|
int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
|
|
{
|
|
struct pci_dev *pdev = device->pdev;
|
|
struct dma_device *dma;
|
|
struct dma_chan *c;
|
|
struct ioat_chan_common *chan;
|
|
int err;
|
|
|
|
device->enumerate_channels = ioat2_enumerate_channels;
|
|
device->reset_hw = ioat2_reset_hw;
|
|
device->cleanup_fn = ioat2_cleanup_event;
|
|
device->timer_fn = ioat2_timer_event;
|
|
device->self_test = ioat_dma_self_test;
|
|
dma = &device->common;
|
|
dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
|
|
dma->device_issue_pending = ioat2_issue_pending;
|
|
dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
|
|
dma->device_free_chan_resources = ioat2_free_chan_resources;
|
|
dma->device_tx_status = ioat_dma_tx_status;
|
|
|
|
err = ioat_probe(device);
|
|
if (err)
|
|
return err;
|
|
ioat_set_tcp_copy_break(2048);
|
|
|
|
list_for_each_entry(c, &dma->channels, device_node) {
|
|
chan = to_chan_common(c);
|
|
writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
|
|
chan->reg_base + IOAT_DCACTRL_OFFSET);
|
|
}
|
|
|
|
err = ioat_register(device);
|
|
if (err)
|
|
return err;
|
|
|
|
ioat_kobject_add(device, &ioat2_ktype);
|
|
|
|
if (dca)
|
|
device->dca = ioat2_dca_init(pdev, device->reg_base);
|
|
|
|
return err;
|
|
}
|