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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fab957c11e
This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
166 lines
3.3 KiB
C
166 lines
3.3 KiB
C
/*
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ASM_RISCV_SPINLOCK_H
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#define _ASM_RISCV_SPINLOCK_H
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#include <linux/kernel.h>
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#include <asm/current.h>
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/*
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* Simple spin lock operations. These provide no fairness guarantees.
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*/
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/* FIXME: Replace this with a ticket lock, like MIPS. */
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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#define arch_spin_is_locked(x) ((x)->lock != 0)
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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__asm__ __volatile__ (
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"amoswap.w.rl x0, x0, %0"
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: "=A" (lock->lock)
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:: "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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int tmp = 1, busy;
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__asm__ __volatile__ (
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"amoswap.w.aq %0, %2, %1"
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: "=r" (busy), "+A" (lock->lock)
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: "r" (tmp)
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: "memory");
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return !busy;
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}
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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while (1) {
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if (arch_spin_is_locked(lock))
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continue;
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if (arch_spin_trylock(lock))
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break;
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}
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}
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static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
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{
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smp_rmb();
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do {
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cpu_relax();
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} while (arch_spin_is_locked(lock));
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smp_acquire__after_ctrl_dep();
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}
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/***********************************************************/
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static inline int arch_read_can_lock(arch_rwlock_t *lock)
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{
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return lock->lock >= 0;
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}
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static inline int arch_write_can_lock(arch_rwlock_t *lock)
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{
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return lock->lock == 0;
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}
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static inline void arch_read_lock(arch_rwlock_t *lock)
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{
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int tmp;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bltz %1, 1b\n"
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" addi %1, %1, 1\n"
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" sc.w.aq %1, %1, %0\n"
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" bnez %1, 1b\n"
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: "+A" (lock->lock), "=&r" (tmp)
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:: "memory");
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}
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static inline void arch_write_lock(arch_rwlock_t *lock)
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{
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int tmp;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bnez %1, 1b\n"
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" li %1, -1\n"
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" sc.w.aq %1, %1, %0\n"
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" bnez %1, 1b\n"
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: "+A" (lock->lock), "=&r" (tmp)
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:: "memory");
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}
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static inline int arch_read_trylock(arch_rwlock_t *lock)
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{
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int busy;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bltz %1, 1f\n"
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" addi %1, %1, 1\n"
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" sc.w.aq %1, %1, %0\n"
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" bnez %1, 1b\n"
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"1:\n"
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: "+A" (lock->lock), "=&r" (busy)
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:: "memory");
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return !busy;
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}
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static inline int arch_write_trylock(arch_rwlock_t *lock)
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{
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int busy;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bnez %1, 1f\n"
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" li %1, -1\n"
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" sc.w.aq %1, %1, %0\n"
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" bnez %1, 1b\n"
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"1:\n"
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: "+A" (lock->lock), "=&r" (busy)
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:: "memory");
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return !busy;
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}
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static inline void arch_read_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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"amoadd.w.rl x0, %1, %0"
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: "+A" (lock->lock)
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: "r" (-1)
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: "memory");
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}
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static inline void arch_write_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__ (
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"amoswap.w.rl x0, x0, %0"
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: "=A" (lock->lock)
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:: "memory");
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}
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#endif /* _ASM_RISCV_SPINLOCK_H */
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