mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 19:09:39 +07:00
faa392181a
core: - uapi: error out EBUSY when existing master - uapi: rework SET/DROP MASTER permission handling - remove drm_pci.h - drm_pci* are now legacy - introduced managed DRM resources - subclassing support for drm_framebuffer - simple encoder helper - edid improvements - vblank + writeback documentation improved - drm/mm - optimise tree searches - port drivers to use devm_drm_dev_alloc dma-buf: - add flag for p2p buffer support mst: - ACT timeout improvements - remove drm_dp_mst_has_audio - don't use 2nd TX slot - spec recommends against it bridge: - dw-hdmi various improvements - chrontel ch7033 support - fix stack issues with old gcc hdmi: - add unpack function for drm infoframe fbdev: - misc fbdev driver fixes i915: - uapi: global sseu pinning - uapi: OA buffer polling - uapi: remove generated perf code - uapi: per-engine default property values in sysfs - Tigerlake GEN12 enabled. - Lots of gem refactoring - Tigerlake enablement patches - move to drm_device logging - Icelake gamma HW readout - push MST link retrain to hotplug work - bandwidth atomic helpers - ICL fixes - RPS/GT refactoring - Cherryview full-ppgtt support - i915 locking guidelines documented - require linear fb stride to be 512 multiple on gen9 - Tigerlake SAGV support amdgpu: - uapi: encrypted GPU memory handling - uapi: add MEM_SYNC IB flag - p2p dma-buf support - export VRAM dma-bufs - FRU chip access support - RAS/SR-IOV updates - Powerplay locking fixes - VCN DPG (powergating) enablement - GFX10 clockgating fixes - DC fixes - GPU reset fixes - navi SDMA fix - expose FP16 for modesetting - DP 1.4 compliance fixes - gfx10 soft recovery - Improved Critical Thermal Faults handling - resizable BAR on gmc10 amdkfd: - uapi: GWS resource management - track GPU memory per process - report PCI domain in topology radeon: - safe reg list generator fixes nouveau: - HD audio fixes on recent systems - vGPU detection (fail probe if we're on one, for now) - Interlaced mode fixes (mostly avoidance on Turing, which doesn't support it) - SVM improvements/fixes - NVIDIA format modifier support - Misc other fixes. adv7511: - HDMI SPDIF support ast: - allocate crtc state size - fix double assignment - fix suspend bochs: - drop connector register cirrus: - move to tiny drivers. exynos: - fix imported dma-buf mapping - enable runtime PM - fixes and cleanups mediatek: - DPI pin mode swap - config mipi_tx current/impedance lima: - devfreq + cooling device support - task handling improvements - runtime PM support pl111: - vexpress init improvements - fix module auto-load rcar-du: - DT bindings conversion to YAML - Planes zpos sanity check and fix - MAINTAINERS entry for LVDS panel driver mcde: - fix return value mgag200: - use managed config init stm: - read endpoints from DT vboxvideo: - use PCI managed functions - drop WC mtrr vkms: - enable cursor by default rockchip: - afbc support virtio: - various cleanups qxl: - fix cursor notify port hisilicon: - 128-byte stride alignment fix sun4i: - improved format handling -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJe1edsAAoJEAx081l5xIa+bKEQAJAZv/8OMM2rx+p+GyKgrNpl ihTX/oyToy8dw97s1kWF7V5kKU+qjF8aWlKoPS0xovzaMAzYSFz9FRNEUgqtTXMI zIAzSXioqP21oL9/ZTHcXDULtz8Gk3uiPomgXMWLlNBdt3X5qvCwsmPRIYSwG0GJ 00VCvxDbVxGSM3wzcvbfyRwHCq3SrFvIusXv5jHnnxEFGH0C7Mj2/FLYMKLNjvli Q8VEI2wQPZj1QdA8fLFVneIQsR6YUSko9OfFMANP8VJGpPMnUkvVxTJ5ACGJspvn U/h6NYqJeUU2Y3BSKqtjIC3a1LY51tp5tL9q4H9TD1hqMckt6F2V7T2IeFU8i6+V YzUsSiT4q1xB+uiFVcgopx2hyIp8INOEyWrVdYgw2JviROeRD+pDHvJd13ZNMnTe GvLWQ/PfBFrcz8eligjiYjOf66ZTU+j/rivaOBFyrs9gdlsaEW2QRurFrcNX+0lZ kDbLsIFjhYnPXsvHP87x4BuQCKQIEh8wWuxXuJjunBPdqVrJyltZWbBiKO571b5/ BtX6xj6ztUOffR2RdiVanzY546I2hEi7SHMUuWnMqXsOV46GBN0QvlpZad/47n9x ZUy8HDDD0/qWuGwvPOJGIeAnUteWge9AhWXTeN5+1h5m+QEOzYkPKqC3Hp8TW1pM gToTWgAhnu731fhzLWyt =H7IS -----END PGP SIGNATURE----- Merge tag 'drm-next-2020-06-02' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "Highlights: - Core DRM had a lot of refactoring around managed drm resources to make drivers simpler. - Intel Tigerlake support is on by default - amdgpu now support p2p PCI buffer sharing and encrypted GPU memory Details: core: - uapi: error out EBUSY when existing master - uapi: rework SET/DROP MASTER permission handling - remove drm_pci.h - drm_pci* are now legacy - introduced managed DRM resources - subclassing support for drm_framebuffer - simple encoder helper - edid improvements - vblank + writeback documentation improved - drm/mm - optimise tree searches - port drivers to use devm_drm_dev_alloc dma-buf: - add flag for p2p buffer support mst: - ACT timeout improvements - remove drm_dp_mst_has_audio - don't use 2nd TX slot - spec recommends against it bridge: - dw-hdmi various improvements - chrontel ch7033 support - fix stack issues with old gcc hdmi: - add unpack function for drm infoframe fbdev: - misc fbdev driver fixes i915: - uapi: global sseu pinning - uapi: OA buffer polling - uapi: remove generated perf code - uapi: per-engine default property values in sysfs - Tigerlake GEN12 enabled. - Lots of gem refactoring - Tigerlake enablement patches - move to drm_device logging - Icelake gamma HW readout - push MST link retrain to hotplug work - bandwidth atomic helpers - ICL fixes - RPS/GT refactoring - Cherryview full-ppgtt support - i915 locking guidelines documented - require linear fb stride to be 512 multiple on gen9 - Tigerlake SAGV support amdgpu: - uapi: encrypted GPU memory handling - uapi: add MEM_SYNC IB flag - p2p dma-buf support - export VRAM dma-bufs - FRU chip access support - RAS/SR-IOV updates - Powerplay locking fixes - VCN DPG (powergating) enablement - GFX10 clockgating fixes - DC fixes - GPU reset fixes - navi SDMA fix - expose FP16 for modesetting - DP 1.4 compliance fixes - gfx10 soft recovery - Improved Critical Thermal Faults handling - resizable BAR on gmc10 amdkfd: - uapi: GWS resource management - track GPU memory per process - report PCI domain in topology radeon: - safe reg list generator fixes nouveau: - HD audio fixes on recent systems - vGPU detection (fail probe if we're on one, for now) - Interlaced mode fixes (mostly avoidance on Turing, which doesn't support it) - SVM improvements/fixes - NVIDIA format modifier support - Misc other fixes. adv7511: - HDMI SPDIF support ast: - allocate crtc state size - fix double assignment - fix suspend bochs: - drop connector register cirrus: - move to tiny drivers. exynos: - fix imported dma-buf mapping - enable runtime PM - fixes and cleanups mediatek: - DPI pin mode swap - config mipi_tx current/impedance lima: - devfreq + cooling device support - task handling improvements - runtime PM support pl111: - vexpress init improvements - fix module auto-load rcar-du: - DT bindings conversion to YAML - Planes zpos sanity check and fix - MAINTAINERS entry for LVDS panel driver mcde: - fix return value mgag200: - use managed config init stm: - read endpoints from DT vboxvideo: - use PCI managed functions - drop WC mtrr vkms: - enable cursor by default rockchip: - afbc support virtio: - various cleanups qxl: - fix cursor notify port hisilicon: - 128-byte stride alignment fix sun4i: - improved format handling" * tag 'drm-next-2020-06-02' of git://anongit.freedesktop.org/drm/drm: (1401 commits) drm/amd/display: Fix potential integer wraparound resulting in a hang drm/amd/display: drop cursor position check in atomic test drm/amdgpu: fix device attribute node create failed with multi gpu drm/nouveau: use correct conflicting framebuffer API drm/vblank: Fix -Wformat compile warnings on some arches drm/amdgpu: Sync with VM root BO when switching VM to CPU update mode drm/amd/display: Handle GPU reset for DC block drm/amdgpu: add apu flags (v2) drm/amd/powerpay: Disable gfxoff when setting manual mode on picasso and raven drm/amdgpu: fix pm sysfs node handling (v2) drm/amdgpu: move gpu_info parsing after common early init drm/amdgpu: move discovery gfx config fetching drm/nouveau/dispnv50: fix runtime pm imbalance on error drm/nouveau: fix runtime pm imbalance on error drm/nouveau: fix runtime pm imbalance on error drm/nouveau/debugfs: fix runtime pm imbalance on error drm/nouveau/nouveau/hmm: fix migrate zero page to GPU drm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocations drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST drm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes() ...
526 lines
13 KiB
C
526 lines
13 KiB
C
/*
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* Copyright (C) 2015 Red Hat, Inc.
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* All Rights Reserved.
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*
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* Authors:
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* Dave Airlie
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* Alon Levy
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/file.h>
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#include <linux/sync_file.h>
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#include <linux/uaccess.h>
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#include <drm/drm_file.h>
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#include <drm/virtgpu_drm.h>
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#include "virtgpu_drv.h"
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void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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char dbgname[TASK_COMM_LEN];
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mutex_lock(&vfpriv->context_lock);
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if (vfpriv->context_created)
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goto out_unlock;
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get_task_comm(dbgname, current);
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virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
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strlen(dbgname), dbgname);
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vfpriv->context_created = true;
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out_unlock:
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mutex_unlock(&vfpriv->context_lock);
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}
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static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_map *virtio_gpu_map = data;
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return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev,
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virtio_gpu_map->handle,
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&virtio_gpu_map->offset);
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}
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/*
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* Usage of execbuffer:
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* Relocations need to take into account the full VIRTIO_GPUDrawable size.
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* However, the command as passed from user space must *not* contain the initial
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* VIRTIO_GPUReleaseInfo struct (first XXX bytes)
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*/
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static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_virtgpu_execbuffer *exbuf = data;
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct virtio_gpu_fence *out_fence;
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int ret;
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uint32_t *bo_handles = NULL;
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void __user *user_bo_handles = NULL;
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struct virtio_gpu_object_array *buflist = NULL;
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struct sync_file *sync_file;
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int in_fence_fd = exbuf->fence_fd;
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int out_fence_fd = -1;
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void *buf;
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if (vgdev->has_virgl_3d == false)
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return -ENOSYS;
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if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
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return -EINVAL;
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exbuf->fence_fd = -1;
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virtio_gpu_create_context(dev, file);
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if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
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struct dma_fence *in_fence;
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in_fence = sync_file_get_fence(in_fence_fd);
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if (!in_fence)
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return -EINVAL;
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/*
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* Wait if the fence is from a foreign context, or if the fence
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* array contains any fence from a foreign context.
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*/
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ret = 0;
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if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context))
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ret = dma_fence_wait(in_fence, true);
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dma_fence_put(in_fence);
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if (ret)
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return ret;
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}
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if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
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out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
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if (out_fence_fd < 0)
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return out_fence_fd;
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}
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if (exbuf->num_bo_handles) {
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bo_handles = kvmalloc_array(exbuf->num_bo_handles,
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sizeof(uint32_t), GFP_KERNEL);
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if (!bo_handles) {
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ret = -ENOMEM;
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goto out_unused_fd;
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}
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user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
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if (copy_from_user(bo_handles, user_bo_handles,
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exbuf->num_bo_handles * sizeof(uint32_t))) {
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ret = -EFAULT;
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goto out_unused_fd;
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}
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buflist = virtio_gpu_array_from_handles(file, bo_handles,
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exbuf->num_bo_handles);
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if (!buflist) {
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ret = -ENOENT;
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goto out_unused_fd;
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}
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kvfree(bo_handles);
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bo_handles = NULL;
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}
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buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
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if (IS_ERR(buf)) {
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ret = PTR_ERR(buf);
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goto out_unused_fd;
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}
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if (buflist) {
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ret = virtio_gpu_array_lock_resv(buflist);
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if (ret)
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goto out_memdup;
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}
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out_fence = virtio_gpu_fence_alloc(vgdev);
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if(!out_fence) {
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ret = -ENOMEM;
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goto out_unresv;
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}
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if (out_fence_fd >= 0) {
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sync_file = sync_file_create(&out_fence->f);
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if (!sync_file) {
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dma_fence_put(&out_fence->f);
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ret = -ENOMEM;
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goto out_memdup;
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}
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exbuf->fence_fd = out_fence_fd;
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fd_install(out_fence_fd, sync_file->file);
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}
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virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
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vfpriv->ctx_id, buflist, out_fence);
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virtio_gpu_notify(vgdev);
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return 0;
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out_unresv:
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if (buflist)
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virtio_gpu_array_unlock_resv(buflist);
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out_memdup:
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kvfree(buf);
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out_unused_fd:
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kvfree(bo_handles);
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if (buflist)
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virtio_gpu_array_put_free(buflist);
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if (out_fence_fd >= 0)
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put_unused_fd(out_fence_fd);
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return ret;
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}
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static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_getparam *param = data;
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int value;
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switch (param->param) {
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case VIRTGPU_PARAM_3D_FEATURES:
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value = vgdev->has_virgl_3d == true ? 1 : 0;
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break;
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case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
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value = 1;
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break;
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default:
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return -EINVAL;
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}
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if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
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return -EFAULT;
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return 0;
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}
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static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_resource_create *rc = data;
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struct virtio_gpu_fence *fence;
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int ret;
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struct virtio_gpu_object *qobj;
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struct drm_gem_object *obj;
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uint32_t handle = 0;
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struct virtio_gpu_object_params params = { 0 };
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if (vgdev->has_virgl_3d) {
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virtio_gpu_create_context(dev, file);
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params.virgl = true;
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params.target = rc->target;
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params.bind = rc->bind;
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params.depth = rc->depth;
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params.array_size = rc->array_size;
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params.last_level = rc->last_level;
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params.nr_samples = rc->nr_samples;
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params.flags = rc->flags;
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} else {
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if (rc->depth > 1)
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return -EINVAL;
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if (rc->nr_samples > 1)
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return -EINVAL;
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if (rc->last_level > 1)
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return -EINVAL;
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if (rc->target != 2)
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return -EINVAL;
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if (rc->array_size > 1)
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return -EINVAL;
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}
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params.format = rc->format;
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params.width = rc->width;
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params.height = rc->height;
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params.size = rc->size;
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/* allocate a single page size object */
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if (params.size == 0)
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params.size = PAGE_SIZE;
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fence = virtio_gpu_fence_alloc(vgdev);
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if (!fence)
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return -ENOMEM;
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ret = virtio_gpu_object_create(vgdev, ¶ms, &qobj, fence);
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dma_fence_put(&fence->f);
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if (ret < 0)
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return ret;
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obj = &qobj->base.base;
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ret = drm_gem_handle_create(file, obj, &handle);
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if (ret) {
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drm_gem_object_release(obj);
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return ret;
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}
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drm_gem_object_put_unlocked(obj);
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rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
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rc->bo_handle = handle;
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return 0;
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}
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static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_virtgpu_resource_info *ri = data;
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struct drm_gem_object *gobj = NULL;
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struct virtio_gpu_object *qobj = NULL;
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gobj = drm_gem_object_lookup(file, ri->bo_handle);
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if (gobj == NULL)
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return -ENOENT;
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qobj = gem_to_virtio_gpu_obj(gobj);
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ri->size = qobj->base.base.size;
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ri->res_handle = qobj->hw_res_handle;
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drm_gem_object_put_unlocked(gobj);
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return 0;
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}
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static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
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void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct drm_virtgpu_3d_transfer_from_host *args = data;
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struct virtio_gpu_object_array *objs;
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struct virtio_gpu_fence *fence;
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int ret;
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u32 offset = args->offset;
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if (vgdev->has_virgl_3d == false)
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return -ENOSYS;
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virtio_gpu_create_context(dev, file);
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objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
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if (objs == NULL)
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return -ENOENT;
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ret = virtio_gpu_array_lock_resv(objs);
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if (ret != 0)
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goto err_put_free;
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fence = virtio_gpu_fence_alloc(vgdev);
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if (!fence) {
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ret = -ENOMEM;
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goto err_unlock;
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}
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virtio_gpu_cmd_transfer_from_host_3d
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(vgdev, vfpriv->ctx_id, offset, args->level,
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&args->box, objs, fence);
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dma_fence_put(&fence->f);
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virtio_gpu_notify(vgdev);
|
|
return 0;
|
|
|
|
err_unlock:
|
|
virtio_gpu_array_unlock_resv(objs);
|
|
err_put_free:
|
|
virtio_gpu_array_put_free(objs);
|
|
return ret;
|
|
}
|
|
|
|
static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct virtio_gpu_device *vgdev = dev->dev_private;
|
|
struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
|
|
struct drm_virtgpu_3d_transfer_to_host *args = data;
|
|
struct virtio_gpu_object_array *objs;
|
|
struct virtio_gpu_fence *fence;
|
|
int ret;
|
|
u32 offset = args->offset;
|
|
|
|
objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
|
|
if (objs == NULL)
|
|
return -ENOENT;
|
|
|
|
if (!vgdev->has_virgl_3d) {
|
|
virtio_gpu_cmd_transfer_to_host_2d
|
|
(vgdev, offset,
|
|
args->box.w, args->box.h, args->box.x, args->box.y,
|
|
objs, NULL);
|
|
} else {
|
|
virtio_gpu_create_context(dev, file);
|
|
ret = virtio_gpu_array_lock_resv(objs);
|
|
if (ret != 0)
|
|
goto err_put_free;
|
|
|
|
ret = -ENOMEM;
|
|
fence = virtio_gpu_fence_alloc(vgdev);
|
|
if (!fence)
|
|
goto err_unlock;
|
|
|
|
virtio_gpu_cmd_transfer_to_host_3d
|
|
(vgdev,
|
|
vfpriv ? vfpriv->ctx_id : 0, offset,
|
|
args->level, &args->box, objs, fence);
|
|
dma_fence_put(&fence->f);
|
|
}
|
|
virtio_gpu_notify(vgdev);
|
|
return 0;
|
|
|
|
err_unlock:
|
|
virtio_gpu_array_unlock_resv(objs);
|
|
err_put_free:
|
|
virtio_gpu_array_put_free(objs);
|
|
return ret;
|
|
}
|
|
|
|
static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_virtgpu_3d_wait *args = data;
|
|
struct drm_gem_object *obj;
|
|
long timeout = 15 * HZ;
|
|
int ret;
|
|
|
|
obj = drm_gem_object_lookup(file, args->handle);
|
|
if (obj == NULL)
|
|
return -ENOENT;
|
|
|
|
if (args->flags & VIRTGPU_WAIT_NOWAIT) {
|
|
ret = dma_resv_test_signaled_rcu(obj->resv, true);
|
|
} else {
|
|
ret = dma_resv_wait_timeout_rcu(obj->resv, true, true,
|
|
timeout);
|
|
}
|
|
if (ret == 0)
|
|
ret = -EBUSY;
|
|
else if (ret > 0)
|
|
ret = 0;
|
|
|
|
drm_gem_object_put_unlocked(obj);
|
|
return ret;
|
|
}
|
|
|
|
static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
|
|
void *data, struct drm_file *file)
|
|
{
|
|
struct virtio_gpu_device *vgdev = dev->dev_private;
|
|
struct drm_virtgpu_get_caps *args = data;
|
|
unsigned size, host_caps_size;
|
|
int i;
|
|
int found_valid = -1;
|
|
int ret;
|
|
struct virtio_gpu_drv_cap_cache *cache_ent;
|
|
void *ptr;
|
|
|
|
if (vgdev->num_capsets == 0)
|
|
return -ENOSYS;
|
|
|
|
/* don't allow userspace to pass 0 */
|
|
if (args->size == 0)
|
|
return -EINVAL;
|
|
|
|
spin_lock(&vgdev->display_info_lock);
|
|
for (i = 0; i < vgdev->num_capsets; i++) {
|
|
if (vgdev->capsets[i].id == args->cap_set_id) {
|
|
if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
|
|
found_valid = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (found_valid == -1) {
|
|
spin_unlock(&vgdev->display_info_lock);
|
|
return -EINVAL;
|
|
}
|
|
|
|
host_caps_size = vgdev->capsets[found_valid].max_size;
|
|
/* only copy to user the minimum of the host caps size or the guest caps size */
|
|
size = min(args->size, host_caps_size);
|
|
|
|
list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
|
|
if (cache_ent->id == args->cap_set_id &&
|
|
cache_ent->version == args->cap_set_ver) {
|
|
spin_unlock(&vgdev->display_info_lock);
|
|
goto copy_exit;
|
|
}
|
|
}
|
|
spin_unlock(&vgdev->display_info_lock);
|
|
|
|
/* not in cache - need to talk to hw */
|
|
virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
|
|
&cache_ent);
|
|
virtio_gpu_notify(vgdev);
|
|
|
|
copy_exit:
|
|
ret = wait_event_timeout(vgdev->resp_wq,
|
|
atomic_read(&cache_ent->is_valid), 5 * HZ);
|
|
if (!ret)
|
|
return -EBUSY;
|
|
|
|
/* is_valid check must proceed before copy of the cache entry. */
|
|
smp_rmb();
|
|
|
|
ptr = cache_ent->caps_cache;
|
|
|
|
if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
|
|
virtio_gpu_resource_create_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
/* make transfer async to the main ring? - no sure, can we
|
|
* thread these in the underlying GL
|
|
*/
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
|
|
virtio_gpu_transfer_from_host_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
|
|
virtio_gpu_transfer_to_host_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
|
|
DRM_RENDER_ALLOW),
|
|
};
|