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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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48084c3595
Selecting PERF_EVENTS without selecting RISCV_BASE_PMU results in a build
error.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[Palmer: commit text]
Fixes: 178e9fc47aae("perf: riscv: preliminary RISC-V support")
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
86 lines
2.2 KiB
C
86 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 SiFive
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* Copyright (C) 2018 Andes Technology Corporation
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*
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*/
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#ifndef _ASM_RISCV_PERF_EVENT_H
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#define _ASM_RISCV_PERF_EVENT_H
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#include <linux/perf_event.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#ifdef CONFIG_RISCV_BASE_PMU
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#define RISCV_BASE_COUNTERS 2
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/*
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* The RISCV_MAX_COUNTERS parameter should be specified.
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*/
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#define RISCV_MAX_COUNTERS 2
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/*
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* These are the indexes of bits in counteren register *minus* 1,
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* except for cycle. It would be coherent if it can directly mapped
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* to counteren bit definition, but there is a *time* register at
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* counteren[1]. Per-cpu structure is scarce resource here.
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*
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* According to the spec, an implementation can support counter up to
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* mhpmcounter31, but many high-end processors has at most 6 general
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* PMCs, we give the definition to MHPMCOUNTER8 here.
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*/
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#define RISCV_PMU_CYCLE 0
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#define RISCV_PMU_INSTRET 1
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#define RISCV_PMU_MHPMCOUNTER3 2
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#define RISCV_PMU_MHPMCOUNTER4 3
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#define RISCV_PMU_MHPMCOUNTER5 4
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#define RISCV_PMU_MHPMCOUNTER6 5
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#define RISCV_PMU_MHPMCOUNTER7 6
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#define RISCV_PMU_MHPMCOUNTER8 7
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#define RISCV_OP_UNSUPP (-EOPNOTSUPP)
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struct cpu_hw_events {
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/* # currently enabled events*/
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int n_events;
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/* currently enabled events */
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struct perf_event *events[RISCV_MAX_COUNTERS];
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/* vendor-defined PMU data */
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void *platform;
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};
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struct riscv_pmu {
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struct pmu *pmu;
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/* generic hw/cache events table */
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const int *hw_events;
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const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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/* method used to map hw/cache events */
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int (*map_hw_event)(u64 config);
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int (*map_cache_event)(u64 config);
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/* max generic hw events in map */
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int max_events;
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/* number total counters, 2(base) + x(general) */
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int num_counters;
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/* the width of the counter */
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int counter_width;
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/* vendor-defined PMU features */
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void *platform;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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int irq;
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};
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#endif
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#ifdef CONFIG_PERF_EVENTS
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#define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs
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#endif
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#endif /* _ASM_RISCV_PERF_EVENT_H */
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