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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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02b2ee16cc
This patch implements timer and time. RTC and PWM device drivers are also here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
149 lines
3.3 KiB
C
149 lines
3.3 KiB
C
/*
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* linux/arch/unicore32/kernel/time.c
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
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* Copyright (C) 2001-2010 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/timex.h>
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#include <linux/clockchips.h>
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#include <mach/hardware.h>
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#define MIN_OSCR_DELTA 2
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static irqreturn_t puv3_ost0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *c = dev_id;
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/* Disarm the compare/match, signal the event. */
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OST_OIER &= ~OST_OIER_E0;
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OST_OSSR &= ~OST_OSSR_M0;
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c->event_handler(c);
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return IRQ_HANDLED;
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}
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static int
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puv3_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
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{
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unsigned long next, oscr;
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OST_OIER |= OST_OIER_E0;
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next = OST_OSCR + delta;
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OST_OSMR0 = next;
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oscr = OST_OSCR;
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return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
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}
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static void
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puv3_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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OST_OIER &= ~OST_OIER_E0;
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OST_OSSR &= ~OST_OSSR_M0;
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break;
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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}
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}
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static struct clock_event_device ckevt_puv3_osmr0 = {
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.name = "osmr0",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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#ifdef CONFIG_ARCH_FPGA
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.shift = 18, /* correct shift val: 16, but warn_on_slowpath */
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#else
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.shift = 30,
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#endif
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.rating = 200,
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.set_next_event = puv3_osmr0_set_next_event,
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.set_mode = puv3_osmr0_set_mode,
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};
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static cycle_t puv3_read_oscr(struct clocksource *cs)
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{
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return OST_OSCR;
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}
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static struct clocksource cksrc_puv3_oscr = {
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.name = "oscr",
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.rating = 200,
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.read = puv3_read_oscr,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static struct irqaction puv3_timer_irq = {
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.name = "ost0",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = puv3_ost0_interrupt,
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.dev_id = &ckevt_puv3_osmr0,
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};
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void __init time_init(void)
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{
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OST_OIER = 0; /* disable any timer interrupts */
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OST_OSSR = 0; /* clear status on all timers */
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ckevt_puv3_osmr0.mult =
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div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_puv3_osmr0.shift);
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ckevt_puv3_osmr0.max_delta_ns =
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clockevent_delta2ns(0x7fffffff, &ckevt_puv3_osmr0);
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ckevt_puv3_osmr0.min_delta_ns =
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clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_puv3_osmr0) + 1;
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ckevt_puv3_osmr0.cpumask = cpumask_of(0);
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setup_irq(IRQ_TIMER0, &puv3_timer_irq);
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clocksource_register_hz(&cksrc_puv3_oscr, CLOCK_TICK_RATE);
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clockevents_register_device(&ckevt_puv3_osmr0);
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}
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#ifdef CONFIG_PM
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unsigned long osmr[4], oier;
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void puv3_timer_suspend(void)
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{
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osmr[0] = OST_OSMR0;
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osmr[1] = OST_OSMR1;
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osmr[2] = OST_OSMR2;
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osmr[3] = OST_OSMR3;
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oier = OST_OIER;
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}
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void puv3_timer_resume(void)
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{
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OST_OSSR = 0;
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OST_OSMR0 = osmr[0];
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OST_OSMR1 = osmr[1];
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OST_OSMR2 = osmr[2];
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OST_OSMR3 = osmr[3];
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OST_OIER = oier;
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/*
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* OSMR0 is the system timer: make sure OSCR is sufficiently behind
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*/
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OST_OSCR = OST_OSMR0 - LATCH;
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}
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#else
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void puv3_timer_suspend(void) { };
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void puv3_timer_resume(void) { };
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#endif
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