mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 06:36:42 +07:00
e0f0257044
Before:
total: 6 errors, 5 warnings, 80 lines checked
After:
total: 0 errors, 4 warnings, 82 lines checked
No code changed:
arch/x86/kernel/cpu/mtrr/state.o:
text data bss dec hex filename
313 0 4 317 13d state.o.before
313 0 4 317 13d state.o.after
md5:
a0fbd61096205f9180f0bf45ed386d61 state.o.before.asm
a0fbd61096205f9180f0bf45ed386d61 state.o.after.asm
Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
83 lines
2.0 KiB
C
83 lines
2.0 KiB
C
#include <linux/mm.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include <asm/processor-cyrix.h>
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#include <asm/processor-flags.h>
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#include "mtrr.h"
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/* Put the processor into a state where MTRRs can be safely set */
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void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
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{
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unsigned int cr0;
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/* Disable interrupts locally */
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local_irq_save(ctxt->flags);
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if (use_intel() || is_cpu(CYRIX)) {
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if (cpu_has_pge) {
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ctxt->cr4val = read_cr4();
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write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
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}
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/*
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* Disable and flush caches. Note that wbinvd flushes the TLBs
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* as a side-effect
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*/
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cr0 = read_cr0() | X86_CR0_CD;
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wbinvd();
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write_cr0(cr0);
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wbinvd();
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if (use_intel())
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/* Save MTRR state */
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rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
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else
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/* Cyrix ARRs - everything else were excluded at the top */
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ctxt->ccr3 = getCx86(CX86_CCR3);
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}
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}
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void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
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{
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if (use_intel())
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/* Disable MTRRs, and set the default type to uncached */
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mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
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ctxt->deftype_hi);
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else if (is_cpu(CYRIX))
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/* Cyrix ARRs - everything else were excluded at the top */
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setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
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}
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/* Restore the processor after a set_mtrr_prepare */
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void set_mtrr_done(struct set_mtrr_context *ctxt)
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{
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if (use_intel() || is_cpu(CYRIX)) {
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/* Flush caches and TLBs */
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wbinvd();
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/* Restore MTRRdefType */
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if (use_intel())
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/* Intel (P6) standard MTRRs */
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mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
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else
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/* Cyrix ARRs - everything else was excluded at the top */
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setCx86(CX86_CCR3, ctxt->ccr3);
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/* Enable caches */
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write_cr0(read_cr0() & 0xbfffffff);
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/* Restore value of CR4 */
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if (cpu_has_pge)
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write_cr4(ctxt->cr4val);
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}
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/* Re-enable interrupts locally (if enabled previously) */
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local_irq_restore(ctxt->flags);
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}
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