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ac6b6f4531
Document the device tree bindings for the ARTPEC crypto accelerator on ARTPEC-6 and ARTPEC-7 SoCs. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
17 lines
508 B
Plaintext
17 lines
508 B
Plaintext
Axis crypto engine with PDMA interface.
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Required properties:
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- compatible : Should be one of the following strings:
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"axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
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"axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
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- reg: Base address and size for the PDMA register area.
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- interrupts: Interrupt handle for the PDMA interrupt line.
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Example:
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crypto@f4264000 {
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compatible = "axis,artpec6-crypto";
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reg = <0xf4264000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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