Yoshihiro Shimoda fa2d185f75 dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions ... Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V3U (R8A779A0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>		2020-09-10 16:58:13 +02:00
..
arm
bus
clk	dt: Add additional option bindings for IDT VersaClock	2020-06-22 19:04:58 -07:00
clock	dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions	2020-09-10 16:58:13 +02:00
display
dma	dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA	2020-07-17 11:37:59 +05:30
firmware/imx
gce	dt-binding: gce: add gce header file for mt6779	2020-08-03 23:56:37 -05:00
gpio
i2c
iio	Merge branch 'ib-5.8-jz47xx-ts' into HEAD	2020-07-22 14:36:31 +01:00
input
interconnect
interrupt-controller
leds	leds: add RGB color option, as that is different from multicolor.	2020-08-03 13:26:15 +02:00
mailbox	dt-bindings: mailbox: Add devicetree binding for Qcom IPCC	2020-05-30 18:10:27 -05:00
media
memory	dt-bindings: mediatek: Add bindings for MT6779	2020-07-10 16:13:10 +02:00
mfd
mips
mux	Devicetree updates for v5.9:	2020-08-05 13:02:45 -07:00
net
phy	dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY	2020-06-29 18:48:00 +05:30
pinctrl	This is the bulk of the pin control changes for the v5.9	2020-08-09 12:52:28 -07:00
pmu
power	dt-bindings: power: Add r8a779a0 SYSC power domain definitions	2020-09-10 16:57:34 +02:00
pwm
regulator	Merge series "regulator: mt6397: Implement of_map_mode regulator_desc function" from Anand K Mistry <amistry@google.com>:	2020-07-02 16:45:49 +01:00
reset	Here's some more updates that missed the last pull request because I	2020-08-12 12:19:49 -07:00
reset-controller
soc
sound	ASoC: dt-bindings: q6asm: Add Q6ASM_DAI_{TX_RX, TX, RX} defines	2020-07-27 14:21:09 +01:00
spmi
thermal
usb