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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3b2039b266
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 528x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
315 lines
12 KiB
C
315 lines
12 KiB
C
/****************************************************************************/
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/*
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* m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
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*
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* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef m528xsim_h
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#define m528xsim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m528x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK MCF_CLK
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#include <asm/m52xxacr.h>
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/*
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* Define the 5280/5282 SIM register set addresses.
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*/
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#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_UART1 14 /* Interrupt number for UART1 */
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#define MCFINT_UART2 15 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
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#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
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#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
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#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
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#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
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#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
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#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
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#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
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#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
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#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
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#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
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#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
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#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
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#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
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/*
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* DMA unit base addresses.
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*/
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#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
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#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
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#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
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#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
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#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
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#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
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/*
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* FEC ethernet module.
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*/
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#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
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#define MCFFEC_SIZE0 0x800
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/*
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* QSPI module.
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*/
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#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
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#define MCFQSPI_SIZE 0x40
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#define MCFQSPI_CS0 147
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#define MCFQSPI_CS1 148
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#define MCFQSPI_CS2 149
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#define MCFQSPI_CS3 150
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/*
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* GPIO registers
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*/
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#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000)
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#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001)
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#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002)
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#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003)
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#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004)
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#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005)
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#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006)
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#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007)
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#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008)
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#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009)
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#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A)
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#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B)
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#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C)
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#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D)
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#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E)
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#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F)
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#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010)
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#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011)
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#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014)
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#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015)
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#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016)
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#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017)
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#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018)
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#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019)
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#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A)
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#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B)
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#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C)
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#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D)
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#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E)
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#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F)
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#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020)
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#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021)
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#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022)
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#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023)
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#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024)
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#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025)
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#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028)
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#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029)
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#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A)
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#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B)
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#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C)
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#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D)
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#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E)
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#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F)
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#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030)
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#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031)
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#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032)
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#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033)
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#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034)
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#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035)
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#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036)
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#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037)
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#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038)
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#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039)
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#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028)
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#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029)
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#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A)
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#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B)
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#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C)
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#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D)
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#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E)
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#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F)
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#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030)
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#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031)
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#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032)
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#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033)
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#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034)
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#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035)
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#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036)
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#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037)
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#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038)
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#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039)
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#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C)
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#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D)
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#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E)
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#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F)
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#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040)
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#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041)
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#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042)
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#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043)
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#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044)
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#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045)
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#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046)
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#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047)
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#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048)
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#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049)
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#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A)
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#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B)
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#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C)
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#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D)
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#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
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#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
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#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
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#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
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#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
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#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
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#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
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#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
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#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
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#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
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#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
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/*
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* PIT timer base addresses.
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*/
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#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
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#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
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#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
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#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
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/*
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* Edge Port registers
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*/
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#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
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#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
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#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
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#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
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#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
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#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
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/*
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* Queued ADC registers
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*/
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#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
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#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
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#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
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#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
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/*
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* General Purpose Timers registers
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*/
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#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
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#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
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#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
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#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
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/*
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*
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* definitions for generic gpio support
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*
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*/
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#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */
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#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */
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#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */
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#define MCFGPIO_SETR MCFGPIO_SETA /* set output */
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#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#define MCFGPIO_PIN_MAX 180
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/*
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* Derek Cheung - 6 Feb 2005
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* add I2C and QSPI register definition using Freescale's MCF5282
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*/
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/* set Port AS pin for I2C or UART */
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#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
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/* Port UA Pin Assignment Register (8 Bit) */
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#define MCF5282_GPIO_PUAPAR 0x10005C
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/* Interrupt Mask Register Register Low */
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#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
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/* Interrupt Control Register 7 */
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#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
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/*
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* Reset Control Unit (relative to IPSBAR).
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*/
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#define MCF_RCR 0x110000
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#define MCF_RSR 0x110001
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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/*********************************************************************
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*
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* Inter-IC (I2C) Module
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*
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*********************************************************************/
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/* Read/Write access macros for general use */
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#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
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#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
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#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
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#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
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#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
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/* Bit level definitions and macros */
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#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
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#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
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#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
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#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
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#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
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#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
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#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
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#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
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#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
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#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
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#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
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#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
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#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
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#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
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#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
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#endif /* m528xsim_h */
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