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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f22ed71cd6
The LEON MMU Model (SRMMU) does not implement MMu Table probing in hardware, instead it is implemented in software. However the software implementation does not return the PTE as it should which always results in INVALID entires and the PROM mappings are not inherited as they should during startup. The following patch removes the masking of the PTE. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com> Signed-off-by: David S. Miller <davem@davemloft.net>
261 lines
6.3 KiB
C
261 lines
6.3 KiB
C
/*
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* linux/arch/sparc/mm/leon_m.c
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*
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* Copyright (C) 2004 Konrad Eisele (eiselekd@web.de, konrad@gaisler.com) Gaisler Research
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* Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB
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* Copyright (C) 2009 Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB
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*
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* do srmmu probe in software
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*
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/asi.h>
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#include <asm/leon.h>
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#include <asm/tlbflush.h>
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int leon_flush_during_switch = 1;
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int srmmu_swprobe_trace;
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unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr)
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{
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unsigned int ctxtbl;
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unsigned int pgd, pmd, ped;
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unsigned int ptr;
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unsigned int lvl, pte, paddrbase;
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unsigned int ctx;
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unsigned int paddr_calc;
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paddrbase = 0;
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: trace on\n");
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ctxtbl = srmmu_get_ctable_ptr();
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if (!(ctxtbl)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: srmmu_get_ctable_ptr returned 0=>0\n");
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return 0;
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}
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if (!_pfn_valid(PFN(ctxtbl))) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO
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"swprobe: !_pfn_valid(%x)=>0\n",
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PFN(ctxtbl));
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return 0;
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}
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ctx = srmmu_get_context();
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: --- ctx (%x) ---\n", ctx);
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pgd = LEON_BYPASS_LOAD_PA(ctxtbl + (ctx * 4));
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if (((pgd & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: pgd is entry level 3\n");
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lvl = 3;
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pte = pgd;
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paddrbase = pgd & _SRMMU_PTE_PMASK_LEON;
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goto ready;
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}
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if (((pgd & SRMMU_ET_MASK) != SRMMU_ET_PTD)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: pgd is invalid => 0\n");
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return 0;
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}
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: --- pgd (%x) ---\n", pgd);
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ptr = (pgd & SRMMU_PTD_PMASK) << 4;
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ptr += ((((vaddr) >> LEON_PGD_SH) & LEON_PGD_M) * 4);
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if (!_pfn_valid(PFN(ptr)))
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return 0;
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pmd = LEON_BYPASS_LOAD_PA(ptr);
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if (((pmd & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: pmd is entry level 2\n");
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lvl = 2;
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pte = pmd;
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paddrbase = pmd & _SRMMU_PTE_PMASK_LEON;
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goto ready;
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}
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if (((pmd & SRMMU_ET_MASK) != SRMMU_ET_PTD)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: pmd is invalid => 0\n");
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return 0;
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}
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: --- pmd (%x) ---\n", pmd);
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ptr = (pmd & SRMMU_PTD_PMASK) << 4;
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ptr += (((vaddr >> LEON_PMD_SH) & LEON_PMD_M) * 4);
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if (!_pfn_valid(PFN(ptr))) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: !_pfn_valid(%x)=>0\n",
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PFN(ptr));
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return 0;
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}
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ped = LEON_BYPASS_LOAD_PA(ptr);
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if (((ped & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: ped is entry level 1\n");
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lvl = 1;
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pte = ped;
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paddrbase = ped & _SRMMU_PTE_PMASK_LEON;
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goto ready;
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}
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if (((ped & SRMMU_ET_MASK) != SRMMU_ET_PTD)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: ped is invalid => 0\n");
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return 0;
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}
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: --- ped (%x) ---\n", ped);
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ptr = (ped & SRMMU_PTD_PMASK) << 4;
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ptr += (((vaddr >> LEON_PTE_SH) & LEON_PTE_M) * 4);
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if (!_pfn_valid(PFN(ptr)))
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return 0;
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ptr = LEON_BYPASS_LOAD_PA(ptr);
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if (((ptr & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: ptr is entry level 0\n");
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lvl = 0;
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pte = ptr;
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paddrbase = ptr & _SRMMU_PTE_PMASK_LEON;
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goto ready;
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}
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: ptr is invalid => 0\n");
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return 0;
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ready:
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switch (lvl) {
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case 0:
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paddr_calc =
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(vaddr & ~(-1 << LEON_PTE_SH)) | ((pte & ~0xff) << 4);
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break;
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case 1:
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paddr_calc =
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(vaddr & ~(-1 << LEON_PMD_SH)) | ((pte & ~0xff) << 4);
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break;
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case 2:
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paddr_calc =
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(vaddr & ~(-1 << LEON_PGD_SH)) | ((pte & ~0xff) << 4);
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break;
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default:
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case 3:
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paddr_calc = vaddr;
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break;
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}
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if (srmmu_swprobe_trace)
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printk(KERN_INFO "swprobe: padde %x\n", paddr_calc);
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if (paddr)
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*paddr = paddr_calc;
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return pte;
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}
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void leon_flush_icache_all(void)
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{
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__asm__ __volatile__(" flush "); /*iflush*/
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}
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void leon_flush_dcache_all(void)
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{
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
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"i"(ASI_LEON_DFLUSH) : "memory");
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}
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void leon_flush_pcache_all(struct vm_area_struct *vma, unsigned long page)
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{
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if (vma->vm_flags & VM_EXEC)
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leon_flush_icache_all();
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leon_flush_dcache_all();
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}
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void leon_flush_cache_all(void)
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{
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__asm__ __volatile__(" flush "); /*iflush*/
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
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"i"(ASI_LEON_DFLUSH) : "memory");
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}
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void leon_flush_tlb_all(void)
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{
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leon_flush_cache_all();
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r"(0x400),
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"i"(ASI_LEON_MMUFLUSH) : "memory");
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}
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/* get all cache regs */
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void leon3_getCacheRegs(struct leon3_cacheregs *regs)
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{
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unsigned long ccr, iccr, dccr;
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if (!regs)
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return;
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/* Get Cache regs from "Cache ASI" address 0x0, 0x8 and 0xC */
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__asm__ __volatile__("lda [%%g0] %3, %0\n\t"
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"mov 0x08, %%g1\n\t"
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"lda [%%g1] %3, %1\n\t"
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"mov 0x0c, %%g1\n\t"
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"lda [%%g1] %3, %2\n\t"
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: "=r"(ccr), "=r"(iccr), "=r"(dccr)
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/* output */
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: "i"(ASI_LEON_CACHEREGS) /* input */
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: "g1" /* clobber list */
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);
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regs->ccr = ccr;
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regs->iccr = iccr;
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regs->dccr = dccr;
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}
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/* Due to virtual cache we need to check cache configuration if
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* it is possible to skip flushing in some cases.
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*
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* Leon2 and Leon3 differ in their way of telling cache information
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*
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*/
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int __init leon_flush_needed(void)
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{
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int flush_needed = -1;
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unsigned int ssize, sets;
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char *setStr[4] =
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{ "direct mapped", "2-way associative", "3-way associative",
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"4-way associative"
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};
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/* leon 3 */
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struct leon3_cacheregs cregs;
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leon3_getCacheRegs(&cregs);
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sets = (cregs.dccr & LEON3_XCCR_SETS_MASK) >> 24;
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/* (ssize=>realsize) 0=>1k, 1=>2k, 2=>4k, 3=>8k ... */
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ssize = 1 << ((cregs.dccr & LEON3_XCCR_SSIZE_MASK) >> 20);
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printk(KERN_INFO "CACHE: %s cache, set size %dk\n",
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sets > 3 ? "unknown" : setStr[sets], ssize);
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if ((ssize <= (PAGE_SIZE / 1024)) && (sets == 0)) {
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/* Set Size <= Page size ==>
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flush on every context switch not needed. */
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flush_needed = 0;
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printk(KERN_INFO "CACHE: not flushing on every context switch\n");
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}
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return flush_needed;
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}
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void leon_switch_mm(void)
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{
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flush_tlb_mm((void *)0);
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if (leon_flush_during_switch)
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leon_flush_cache_all();
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}
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