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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f9f3232a7d
While the default ->mmap and ->get_sgtable implementations work for the
majority of our dma_map_ops impementations they are inherently safe
for others that don't use the page allocator or CMA and/or use their
own way of remapping not covered by the common code. So remove the
defaults if these methods are not wired up, but instead wire up the
default implementations for all safe instances.
Fixes: e1c7e32453 ("dma-mapping: always provide the dma_map_ops based implementation")
Signed-off-by: Christoph Hellwig <hch@lst.de>
214 lines
6.4 KiB
C
214 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2006 Benjamin Herrenschmidt, IBM Corporation
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*
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* Provide default implementations of the DMA mapping callbacks for
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* busses using the iommu infrastructure
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*/
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#include <linux/dma-direct.h>
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#include <linux/pci.h>
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#include <asm/iommu.h>
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/*
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* Generic iommu implementation
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*/
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/*
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* The coherent mask may be smaller than the real mask, check if we can
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* really use a direct window.
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*/
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static inline bool dma_iommu_alloc_bypass(struct device *dev)
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{
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return dev->archdata.iommu_bypass && !iommu_fixed_is_weak &&
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dma_direct_supported(dev, dev->coherent_dma_mask);
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}
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static inline bool dma_iommu_map_bypass(struct device *dev,
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unsigned long attrs)
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{
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return dev->archdata.iommu_bypass &&
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(!iommu_fixed_is_weak || (attrs & DMA_ATTR_WEAK_ORDERING));
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}
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/* Allocates a contiguous real buffer and creates mappings over it.
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* Returns the virtual address of the buffer and sets dma_handle
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* to the dma address (mapping) of the first page.
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*/
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static void *dma_iommu_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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unsigned long attrs)
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{
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if (dma_iommu_alloc_bypass(dev))
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return dma_direct_alloc(dev, size, dma_handle, flag, attrs);
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return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size,
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dma_handle, dev->coherent_dma_mask, flag,
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dev_to_node(dev));
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}
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static void dma_iommu_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle,
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unsigned long attrs)
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{
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if (dma_iommu_alloc_bypass(dev))
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dma_direct_free(dev, size, vaddr, dma_handle, attrs);
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else
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iommu_free_coherent(get_iommu_table_base(dev), size, vaddr,
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dma_handle);
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}
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/* Creates TCEs for a user provided buffer. The user buffer must be
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* contiguous real kernel storage (not vmalloc). The address passed here
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* comprises a page address and offset into that page. The dma_addr_t
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* returned will point to the same byte within the page as was passed in.
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*/
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static dma_addr_t dma_iommu_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction,
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unsigned long attrs)
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{
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if (dma_iommu_map_bypass(dev, attrs))
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return dma_direct_map_page(dev, page, offset, size, direction,
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attrs);
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return iommu_map_page(dev, get_iommu_table_base(dev), page, offset,
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size, dma_get_mask(dev), direction, attrs);
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}
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static void dma_iommu_unmap_page(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction,
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unsigned long attrs)
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{
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if (!dma_iommu_map_bypass(dev, attrs))
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iommu_unmap_page(get_iommu_table_base(dev), dma_handle, size,
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direction, attrs);
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else
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dma_direct_unmap_page(dev, dma_handle, size, direction, attrs);
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}
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static int dma_iommu_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction,
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unsigned long attrs)
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{
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if (dma_iommu_map_bypass(dev, attrs))
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return dma_direct_map_sg(dev, sglist, nelems, direction, attrs);
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return ppc_iommu_map_sg(dev, get_iommu_table_base(dev), sglist, nelems,
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dma_get_mask(dev), direction, attrs);
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}
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static void dma_iommu_unmap_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction,
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unsigned long attrs)
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{
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if (!dma_iommu_map_bypass(dev, attrs))
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ppc_iommu_unmap_sg(get_iommu_table_base(dev), sglist, nelems,
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direction, attrs);
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else
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dma_direct_unmap_sg(dev, sglist, nelems, direction, attrs);
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}
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static bool dma_iommu_bypass_supported(struct device *dev, u64 mask)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct pci_controller *phb = pci_bus_to_host(pdev->bus);
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return phb->controller_ops.iommu_bypass_supported &&
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phb->controller_ops.iommu_bypass_supported(pdev, mask);
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}
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/* We support DMA to/from any memory page via the iommu */
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int dma_iommu_dma_supported(struct device *dev, u64 mask)
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{
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struct iommu_table *tbl = get_iommu_table_base(dev);
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if (!tbl) {
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dev_info(dev, "Warning: IOMMU dma not supported: mask 0x%08llx"
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", table unavailable\n", mask);
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return 0;
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}
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if (dev_is_pci(dev) && dma_iommu_bypass_supported(dev, mask)) {
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dev->archdata.iommu_bypass = true;
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dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
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return 1;
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}
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if (tbl->it_offset > (mask >> tbl->it_page_shift)) {
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dev_info(dev, "Warning: IOMMU offset too big for device mask\n");
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dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n",
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mask, tbl->it_offset << tbl->it_page_shift);
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return 0;
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}
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dev_dbg(dev, "iommu: not 64-bit, using default ops\n");
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dev->archdata.iommu_bypass = false;
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return 1;
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}
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u64 dma_iommu_get_required_mask(struct device *dev)
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{
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struct iommu_table *tbl = get_iommu_table_base(dev);
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u64 mask;
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if (!tbl)
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return 0;
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if (dev_is_pci(dev)) {
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u64 bypass_mask = dma_direct_get_required_mask(dev);
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if (dma_iommu_bypass_supported(dev, bypass_mask))
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return bypass_mask;
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}
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mask = 1ULL < (fls_long(tbl->it_offset + tbl->it_size) - 1);
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mask += mask - 1;
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return mask;
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}
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static void dma_iommu_sync_for_cpu(struct device *dev, dma_addr_t addr,
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size_t size, enum dma_data_direction dir)
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{
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if (dma_iommu_alloc_bypass(dev))
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dma_direct_sync_single_for_cpu(dev, addr, size, dir);
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}
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static void dma_iommu_sync_for_device(struct device *dev, dma_addr_t addr,
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size_t sz, enum dma_data_direction dir)
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{
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if (dma_iommu_alloc_bypass(dev))
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dma_direct_sync_single_for_device(dev, addr, sz, dir);
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}
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extern void dma_iommu_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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if (dma_iommu_alloc_bypass(dev))
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dma_direct_sync_sg_for_cpu(dev, sgl, nents, dir);
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}
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extern void dma_iommu_sync_sg_for_device(struct device *dev,
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struct scatterlist *sgl, int nents, enum dma_data_direction dir)
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{
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if (dma_iommu_alloc_bypass(dev))
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dma_direct_sync_sg_for_device(dev, sgl, nents, dir);
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}
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const struct dma_map_ops dma_iommu_ops = {
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.alloc = dma_iommu_alloc_coherent,
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.free = dma_iommu_free_coherent,
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.map_sg = dma_iommu_map_sg,
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.unmap_sg = dma_iommu_unmap_sg,
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.dma_supported = dma_iommu_dma_supported,
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.map_page = dma_iommu_map_page,
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.unmap_page = dma_iommu_unmap_page,
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.get_required_mask = dma_iommu_get_required_mask,
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.sync_single_for_cpu = dma_iommu_sync_for_cpu,
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.sync_single_for_device = dma_iommu_sync_for_device,
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.sync_sg_for_cpu = dma_iommu_sync_sg_for_cpu,
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.sync_sg_for_device = dma_iommu_sync_sg_for_device,
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.mmap = dma_common_mmap,
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.get_sgtable = dma_common_get_sgtable,
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};
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