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The AES loops in arch/sparc/crypto/aes_glue.c use a scheme where the key material is preloaded into the FPU registers, and then we loop over and over doing the crypt operation, reusing those pre-cooked key registers. There are intervening blkcipher*() calls between the crypt operation calls. And those might perform memcpy() and thus also try to use the FPU. The sparc64 kernel FPU usage mechanism is designed to allow such recursive uses, but with a catch. There has to be a trap between the two FPU using threads of control. The mechanism works by, when the FPU is already in use by the kernel, allocating a slot for FPU saving at trap time. Then if, within the trap handler, we try to use the FPU registers, the pre-trap FPU register state is saved into the slot. Then at trap return time we notice this and restore the pre-trap FPU state. Over the long term there are various more involved ways we can make this work, but for a quick fix let's take advantage of the fact that the situation where this happens is very limited. All sparc64 chips that support the crypto instructiosn also are using the Niagara4 memcpy routine, and that routine only uses the FPU for large copies where we can't get the source aligned properly to a multiple of 8 bytes. We look to see if the FPU is already in use in this context, and if so we use the non-large copy path which only uses integer registers. Furthermore, we also limit this special logic to when we are doing kernel copy, rather than a user copy. Signed-off-by: David S. Miller <davem@davemloft.net>
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
#ifndef _SPARC64_VISASM_H
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#define _SPARC64_VISASM_H
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/* visasm.h: FPU saving macros for VIS routines
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*
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
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#define VISEntry \
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rd %fprs, %o5; \
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andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
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be,pt %icc, 297f; \
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sethi %hi(297f), %g7; \
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sethi %hi(VISenter), %g1; \
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jmpl %g1 + %lo(VISenter), %g0; \
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or %g7, %lo(297f), %g7; \
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297: wr %g0, FPRS_FEF, %fprs; \
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#define VISExit \
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wr %g0, 0, %fprs;
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/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
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* Must preserve %o5 between VISEntryHalf and VISExitHalf */
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#define VISEntryHalf \
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rd %fprs, %o5; \
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andcc %o5, FPRS_FEF, %g0; \
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be,pt %icc, 297f; \
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sethi %hi(298f), %g7; \
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sethi %hi(VISenterhalf), %g1; \
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jmpl %g1 + %lo(VISenterhalf), %g0; \
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or %g7, %lo(298f), %g7; \
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clr %o5; \
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297: wr %o5, FPRS_FEF, %fprs; \
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298:
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#define VISEntryHalfFast(fail_label) \
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rd %fprs, %o5; \
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andcc %o5, FPRS_FEF, %g0; \
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be,pt %icc, 297f; \
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nop; \
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ba,a,pt %xcc, fail_label; \
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297: wr %o5, FPRS_FEF, %fprs;
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#define VISExitHalf \
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wr %o5, 0, %fprs;
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#ifndef __ASSEMBLY__
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static inline void save_and_clear_fpu(void) {
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__asm__ __volatile__ (
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" rd %%fprs, %%o5\n"
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" andcc %%o5, %0, %%g0\n"
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" be,pt %%icc, 299f\n"
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" sethi %%hi(298f), %%g7\n"
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" sethi %%hi(VISenter), %%g1\n"
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" jmpl %%g1 + %%lo(VISenter), %%g0\n"
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" or %%g7, %%lo(298f), %%g7\n"
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" 298: wr %%g0, 0, %%fprs\n"
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" 299:\n"
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" " : : "i" (FPRS_FEF|FPRS_DU) :
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"o5", "g1", "g2", "g3", "g7", "cc");
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}
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int vis_emul(struct pt_regs *, unsigned int);
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#endif
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#endif /* _SPARC64_ASI_H */
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