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Document what's going on in asm/backoff.h with a large and descriptive comment. Refer to it above the cpu_relax() definition in asm/processor_64.h Rename the pause patching section to have "3insn" in it's name like the other patching sections do. Based upon feedback from Sam Ravnborg. Signed-off-by: David S. Miller <davem@davemloft.net>
86 lines
2.7 KiB
C
86 lines
2.7 KiB
C
#ifndef _SPARC64_BACKOFF_H
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#define _SPARC64_BACKOFF_H
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/* The macros in this file implement an exponential backoff facility
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* for atomic operations.
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*
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* When multiple threads compete on an atomic operation, it is
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* possible for one thread to be continually denied a successful
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* completion of the compare-and-swap instruction. Heavily
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* threaded cpu implementations like Niagara can compound this
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* problem even further.
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*
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* When an atomic operation fails and needs to be retried, we spin a
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* certain number of times. At each subsequent failure of the same
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* operation we double the spin count, realizing an exponential
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* backoff.
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*
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* When we spin, we try to use an operation that will cause the
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* current cpu strand to block, and therefore make the core fully
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* available to any other other runnable strands. There are two
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* options, based upon cpu capabilities.
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*
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* On all cpus prior to SPARC-T4 we do three dummy reads of the
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* condition code register. Each read blocks the strand for something
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* between 40 and 50 cpu cycles.
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*
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* For SPARC-T4 and later we have a special "pause" instruction
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* available. This is implemented using writes to register %asr27.
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* The cpu will block the number of cycles written into the register,
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* unless a disrupting trap happens first. SPARC-T4 specifically
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* implements pause with a granularity of 8 cycles. Each strand has
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* an internal pause counter which decrements every 8 cycles. So the
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* chip shifts the %asr27 value down by 3 bits, and writes the result
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* into the pause counter. If a value smaller than 8 is written, the
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* chip blocks for 1 cycle.
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*
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* To achieve the same amount of backoff as the three %ccr reads give
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* on earlier chips, we shift the backoff value up by 7 bits. (Three
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* %ccr reads block for about 128 cycles, 1 << 7 == 128) We write the
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* whole amount we want to block into the pause register, rather than
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* loop writing 128 each time.
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*/
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#define BACKOFF_LIMIT (4 * 1024)
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#ifdef CONFIG_SMP
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#define BACKOFF_SETUP(reg) \
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mov 1, reg
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#define BACKOFF_LABEL(spin_label, continue_label) \
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spin_label
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#define BACKOFF_SPIN(reg, tmp, label) \
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mov reg, tmp; \
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88: rd %ccr, %g0; \
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rd %ccr, %g0; \
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rd %ccr, %g0; \
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.section .pause_3insn_patch,"ax";\
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.word 88b; \
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sllx tmp, 7, tmp; \
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wr tmp, 0, %asr27; \
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clr tmp; \
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.previous; \
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brnz,pt tmp, 88b; \
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sub tmp, 1, tmp; \
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set BACKOFF_LIMIT, tmp; \
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cmp reg, tmp; \
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bg,pn %xcc, label; \
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nop; \
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ba,pt %xcc, label; \
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sllx reg, 1, reg;
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#else
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#define BACKOFF_SETUP(reg)
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#define BACKOFF_LABEL(spin_label, continue_label) \
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continue_label
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#define BACKOFF_SPIN(reg, tmp, label)
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#endif
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#endif /* _SPARC64_BACKOFF_H */
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