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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a654730ec1
All these separate directories for each ColdFire CPU SoC varient seems like overkill. The majority of them only contain a single small config file. Move these into the common ColdFire code directory. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/520x/config.c
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*
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* Copyright (C) 2005, Freescale (www.freescale.com)
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* Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
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* Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfgpio.h>
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/***************************************************************************/
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struct mcf_gpio_chip mcf_gpio_chips[] = {
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MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
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MCFGPF(CS, 9, 3),
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MCFGPF(FECI2C, 16, 4),
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MCFGPF(QSPI, 24, 4),
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MCFGPF(TIMER, 32, 4),
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MCFGPF(UART, 40, 8),
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MCFGPF(FECH, 48, 8),
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MCFGPF(FECL, 56, 8),
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};
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unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
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/***************************************************************************/
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m520x_qspi_init(void)
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{
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u16 par;
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/* setup Port QS for QSPI with gpio CS control */
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writeb(0x3f, MCF_GPIO_PAR_QSPI);
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/* make U1CTS and U2RTS gpio for cs_control */
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par = readw(MCF_GPIO_PAR_UART);
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par &= 0x00ff;
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writew(par, MCF_GPIO_PAR_UART);
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}
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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/***************************************************************************/
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static void __init m520x_uarts_init(void)
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{
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u16 par;
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u8 par2;
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/* UART0 and UART1 GPIO pin setup */
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par = readw(MCF_GPIO_PAR_UART);
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par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
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par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
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writew(par, MCF_GPIO_PAR_UART);
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/* UART1 GPIO pin setup */
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par2 = readb(MCF_GPIO_PAR_FECI2C);
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par2 &= ~0x0F;
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par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
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MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
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writeb(par2, MCF_GPIO_PAR_FECI2C);
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}
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/***************************************************************************/
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static void __init m520x_fec_init(void)
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{
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u8 v;
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/* Set multi-function pins to ethernet mode */
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v = readb(MCF_GPIO_PAR_FEC);
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writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
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v = readb(MCF_GPIO_PAR_FECI2C);
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writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_sched_init = hw_timer_init;
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m520x_uarts_init();
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m520x_fec_init();
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m520x_qspi_init();
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#endif
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}
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/***************************************************************************/
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