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e0728b50d4
Power8 supports a large number of events in each susbystem so when a user runs: perf stat -e branch-instructions sleep 1 perf stat -e L1-dcache-loads sleep 1 it is not clear as to which PMU events were monitored. Export the generic hardware and cache perf events for Power8 to sysfs, so users can precisely determine the PMU event monitored by the generic event. Eg: cat /sys/bus/event_source/devices/cpu/events/branch-instructions event=0x10068 $ cat /sys/bus/event_source/devices/cpu/events/L1-dcache-loads event=0x100ee Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
52 lines
1.7 KiB
C
52 lines
1.7 KiB
C
/*
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* Performance counter support for POWER8 processors.
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*
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* Copyright 2014 Sukadev Bhattiprolu, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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/*
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* Power8 event codes.
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*/
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EVENT(PM_CYC, 0x0001e)
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EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
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EVENT(PM_CMPLU_STALL, 0x4000a)
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EVENT(PM_INST_CMPL, 0x00002)
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EVENT(PM_BRU_FIN, 0x10068)
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EVENT(PM_BR_MPRED_CMPL, 0x400f6)
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/* All L1 D cache load references counted at finish, gated by reject */
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EVENT(PM_LD_REF_L1, 0x100ee)
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/* Load Missed L1 */
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EVENT(PM_LD_MISS_L1, 0x3e054)
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/* Store Missed L1 */
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EVENT(PM_ST_MISS_L1, 0x300f0)
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/* L1 cache data prefetches */
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EVENT(PM_L1_PREF, 0x0d8b8)
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/* Instruction fetches from L1 */
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EVENT(PM_INST_FROM_L1, 0x04080)
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/* Demand iCache Miss */
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EVENT(PM_L1_ICACHE_MISS, 0x200fd)
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/* Instruction Demand sectors wriittent into IL1 */
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EVENT(PM_L1_DEMAND_WRITE, 0x0408c)
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/* Instruction prefetch written into IL1 */
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EVENT(PM_IC_PREF_WRITE, 0x0408e)
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/* The data cache was reloaded from local core's L3 due to a demand load */
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EVENT(PM_DATA_FROM_L3, 0x4c042)
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/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
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EVENT(PM_DATA_FROM_L3MISS, 0x300fe)
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/* All successful D-side store dispatches for this thread */
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EVENT(PM_L2_ST, 0x17080)
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/* All successful D-side store dispatches for this thread that were L2 Miss */
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EVENT(PM_L2_ST_MISS, 0x17082)
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/* Total HW L3 prefetches(Load+store) */
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EVENT(PM_L3_PREF_ALL, 0x4e052)
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/* Data PTEG reload */
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EVENT(PM_DTLB_MISS, 0x300fc)
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/* ITLB Reloaded */
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EVENT(PM_ITLB_MISS, 0x400fc)
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