mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 19:15:25 +07:00
f7c34874f0
Implement atomic primitives using exclusive access opcodes available in the recent xtensa cores. Since l32ex/s32ex don't have any memory ordering guarantees don't define __smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
26 lines
594 B
C
26 lines
594 B
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2001 - 2012 Tensilica Inc.
|
|
*/
|
|
|
|
#ifndef _XTENSA_SYSTEM_H
|
|
#define _XTENSA_SYSTEM_H
|
|
|
|
#include <asm/core.h>
|
|
|
|
#define mb() ({ __asm__ __volatile__("memw" : : : "memory"); })
|
|
#define rmb() barrier()
|
|
#define wmb() mb()
|
|
|
|
#if XCHAL_HAVE_S32C1I
|
|
#define __smp_mb__before_atomic() barrier()
|
|
#define __smp_mb__after_atomic() barrier()
|
|
#endif
|
|
|
|
#include <asm-generic/barrier.h>
|
|
|
|
#endif /* _XTENSA_SYSTEM_H */
|