mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 16:27:01 +07:00
f61e64310b
As of commit 205e1b7f51 ("dma-mapping: warn when there is no
coherent_dma_mask") the Freescale FEC driver is issuing the following
warning on driver initialization on ColdFire systems:
WARNING: CPU: 0 PID: 1 at ./include/linux/dma-mapping.h:516 0x40159e20
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 4.16.0-rc7-dirty #4
Stack from 41833dd8:
41833dd8 40259c53 40025534 40279e26 00000003 00000000 4004e514 41827000
400255de 40244e42 00000204 40159e20 00000009 00000000 00000000 4024531d
40159e20 40244e42 00000204 00000000 00000000 00000000 00000007 00000000
00000000 40279e26 4028d040 40226576 4003ae88 40279e26 418273f6 41833ef8
7fffffff 418273f2 41867028 4003c9a2 4180ac6c 00000004 41833f8c 4013e71c
40279e1c 40279e26 40226c16 4013ced2 40279e26 40279e58 4028d040 00000000
Call Trace:
[<40025534>] 0x40025534
[<4004e514>] 0x4004e514
[<400255de>] 0x400255de
[<40159e20>] 0x40159e20
[<40159e20>] 0x40159e20
It is not fatal, the driver and the system continue to function normally.
As per the warning the coherent_dma_mask is not set on this device.
There is nothing special about the DMA memory coherency on this hardware
so we can just set the mask to 32bits in the platform data for the FEC
ethernet devices.
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
537 lines
11 KiB
C
537 lines
11 KiB
C
/*
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* device.c -- common ColdFire SoC device support
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*
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* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <linux/fec.h>
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#include <asm/traps.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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/*
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* All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
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*/
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static struct mcf_platform_uart mcf_uart_platform_data[] = {
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{
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.mapbase = MCFUART_BASE0,
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.irq = MCF_IRQ_UART0,
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},
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{
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.mapbase = MCFUART_BASE1,
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.irq = MCF_IRQ_UART1,
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},
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#ifdef MCFUART_BASE2
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{
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.mapbase = MCFUART_BASE2,
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.irq = MCF_IRQ_UART2,
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},
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#endif
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#ifdef MCFUART_BASE3
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{
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.mapbase = MCFUART_BASE3,
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.irq = MCF_IRQ_UART3,
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},
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#endif
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#ifdef MCFUART_BASE4
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{
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.mapbase = MCFUART_BASE4,
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.irq = MCF_IRQ_UART4,
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},
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#endif
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#ifdef MCFUART_BASE5
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{
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.mapbase = MCFUART_BASE5,
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.irq = MCF_IRQ_UART5,
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},
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#endif
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#ifdef MCFUART_BASE6
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{
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.mapbase = MCFUART_BASE6,
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.irq = MCF_IRQ_UART6,
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},
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#endif
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#ifdef MCFUART_BASE7
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{
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.mapbase = MCFUART_BASE7,
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.irq = MCF_IRQ_UART7,
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},
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#endif
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#ifdef MCFUART_BASE8
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{
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.mapbase = MCFUART_BASE8,
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.irq = MCF_IRQ_UART8,
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},
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#endif
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#ifdef MCFUART_BASE9
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{
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.mapbase = MCFUART_BASE9,
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.irq = MCF_IRQ_UART9,
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},
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#endif
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{ },
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};
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static struct platform_device mcf_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = mcf_uart_platform_data,
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};
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#if IS_ENABLED(CONFIG_FEC)
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#ifdef CONFIG_M5441x
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#define FEC_NAME "enet-fec"
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static struct fec_platform_data fec_pdata = {
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.phy = PHY_INTERFACE_MODE_RMII,
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};
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#define FEC_PDATA (&fec_pdata)
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#else
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#define FEC_NAME "fec"
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#define FEC_PDATA NULL
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#endif
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/*
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* Some ColdFire cores contain the Fast Ethernet Controller (FEC)
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* block. It is Freescale's own hardware block. Some ColdFires
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* have 2 of these.
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*/
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static struct resource mcf_fec0_resources[] = {
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{
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.start = MCFFEC_BASE0,
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.end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_FECRX0,
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.end = MCF_IRQ_FECRX0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECTX0,
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.end = MCF_IRQ_FECTX0,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECENTC0,
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.end = MCF_IRQ_FECENTC0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_fec0 = {
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.name = FEC_NAME,
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.id = 0,
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.num_resources = ARRAY_SIZE(mcf_fec0_resources),
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.resource = mcf_fec0_resources,
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.dev = {
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.dma_mask = &mcf_fec0.dev.coherent_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = FEC_PDATA,
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}
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};
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#ifdef MCFFEC_BASE1
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static struct resource mcf_fec1_resources[] = {
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{
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.start = MCFFEC_BASE1,
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.end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_FECRX1,
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.end = MCF_IRQ_FECRX1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECTX1,
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.end = MCF_IRQ_FECTX1,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = MCF_IRQ_FECENTC1,
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.end = MCF_IRQ_FECENTC1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_fec1 = {
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.name = FEC_NAME,
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.id = 1,
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.num_resources = ARRAY_SIZE(mcf_fec1_resources),
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.resource = mcf_fec1_resources,
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.dev = {
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.dma_mask = &mcf_fec1.dev.coherent_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = FEC_PDATA,
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}
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};
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#endif /* MCFFEC_BASE1 */
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#endif /* CONFIG_FEC */
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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/*
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* The ColdFire QSPI module is an SPI protocol hardware block used
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* on a number of different ColdFire CPUs.
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*/
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static struct resource mcf_qspi_resources[] = {
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{
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.start = MCFQSPI_BASE,
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.end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_QSPI,
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.end = MCF_IRQ_QSPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
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{
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int status;
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status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
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goto fail0;
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}
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status = gpio_direction_output(MCFQSPI_CS0, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
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goto fail1;
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}
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status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
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goto fail1;
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}
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status = gpio_direction_output(MCFQSPI_CS1, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
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goto fail2;
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}
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status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
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goto fail2;
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}
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status = gpio_direction_output(MCFQSPI_CS2, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
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goto fail3;
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}
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#ifdef MCFQSPI_CS3
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status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
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goto fail3;
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}
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status = gpio_direction_output(MCFQSPI_CS3, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
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gpio_free(MCFQSPI_CS3);
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goto fail3;
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}
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#endif
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return 0;
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fail3:
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gpio_free(MCFQSPI_CS2);
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fail2:
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gpio_free(MCFQSPI_CS1);
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fail1:
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gpio_free(MCFQSPI_CS0);
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fail0:
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return status;
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}
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static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
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{
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#ifdef MCFQSPI_CS3
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gpio_free(MCFQSPI_CS3);
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#endif
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gpio_free(MCFQSPI_CS2);
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gpio_free(MCFQSPI_CS1);
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gpio_free(MCFQSPI_CS0);
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}
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static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, cs_high);
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break;
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#ifdef MCFQSPI_CS3
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case 3:
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gpio_set_value(MCFQSPI_CS3, cs_high);
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break;
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#endif
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}
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}
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static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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switch (chip_select) {
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case 0:
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gpio_set_value(MCFQSPI_CS0, !cs_high);
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break;
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case 1:
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gpio_set_value(MCFQSPI_CS1, !cs_high);
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break;
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case 2:
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gpio_set_value(MCFQSPI_CS2, !cs_high);
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break;
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#ifdef MCFQSPI_CS3
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case 3:
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gpio_set_value(MCFQSPI_CS3, !cs_high);
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break;
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#endif
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}
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}
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static struct mcfqspi_cs_control mcf_cs_control = {
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.setup = mcf_cs_setup,
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.teardown = mcf_cs_teardown,
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.select = mcf_cs_select,
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.deselect = mcf_cs_deselect,
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};
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static struct mcfqspi_platform_data mcf_qspi_data = {
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.bus_num = 0,
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.num_chipselect = 4,
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.cs_control = &mcf_cs_control,
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};
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static struct platform_device mcf_qspi = {
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.name = "mcfqspi",
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.id = 0,
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.num_resources = ARRAY_SIZE(mcf_qspi_resources),
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.resource = mcf_qspi_resources,
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.dev.platform_data = &mcf_qspi_data,
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};
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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#if IS_ENABLED(CONFIG_I2C_IMX)
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static struct resource mcf_i2c0_resources[] = {
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{
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.start = MCFI2C_BASE0,
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.end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_I2C0,
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.end = MCF_IRQ_I2C0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_i2c0 = {
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.name = "imx1-i2c",
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.id = 0,
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.num_resources = ARRAY_SIZE(mcf_i2c0_resources),
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.resource = mcf_i2c0_resources,
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};
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#ifdef MCFI2C_BASE1
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static struct resource mcf_i2c1_resources[] = {
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{
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.start = MCFI2C_BASE1,
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.end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_I2C1,
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.end = MCF_IRQ_I2C1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_i2c1 = {
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.name = "imx1-i2c",
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.id = 1,
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.num_resources = ARRAY_SIZE(mcf_i2c1_resources),
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.resource = mcf_i2c1_resources,
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};
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#endif /* MCFI2C_BASE1 */
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#ifdef MCFI2C_BASE2
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static struct resource mcf_i2c2_resources[] = {
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{
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.start = MCFI2C_BASE2,
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.end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_I2C2,
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.end = MCF_IRQ_I2C2,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_i2c2 = {
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.name = "imx1-i2c",
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.id = 2,
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.num_resources = ARRAY_SIZE(mcf_i2c2_resources),
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.resource = mcf_i2c2_resources,
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};
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#endif /* MCFI2C_BASE2 */
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#ifdef MCFI2C_BASE3
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static struct resource mcf_i2c3_resources[] = {
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{
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.start = MCFI2C_BASE3,
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.end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_I2C3,
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.end = MCF_IRQ_I2C3,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_i2c3 = {
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.name = "imx1-i2c",
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.id = 3,
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.num_resources = ARRAY_SIZE(mcf_i2c3_resources),
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.resource = mcf_i2c3_resources,
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};
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#endif /* MCFI2C_BASE3 */
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#ifdef MCFI2C_BASE4
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static struct resource mcf_i2c4_resources[] = {
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{
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.start = MCFI2C_BASE4,
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.end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_I2C4,
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.end = MCF_IRQ_I2C4,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_i2c4 = {
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.name = "imx1-i2c",
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.id = 4,
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.num_resources = ARRAY_SIZE(mcf_i2c4_resources),
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.resource = mcf_i2c4_resources,
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};
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#endif /* MCFI2C_BASE4 */
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#ifdef MCFI2C_BASE5
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static struct resource mcf_i2c5_resources[] = {
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{
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.start = MCFI2C_BASE5,
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.end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCF_IRQ_I2C5,
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.end = MCF_IRQ_I2C5,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device mcf_i2c5 = {
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.name = "imx1-i2c",
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.id = 5,
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.num_resources = ARRAY_SIZE(mcf_i2c5_resources),
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.resource = mcf_i2c5_resources,
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};
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#endif /* MCFI2C_BASE5 */
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#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
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static struct platform_device *mcf_devices[] __initdata = {
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&mcf_uart,
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#if IS_ENABLED(CONFIG_FEC)
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&mcf_fec0,
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#ifdef MCFFEC_BASE1
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&mcf_fec1,
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#endif
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#endif
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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&mcf_qspi,
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#endif
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#if IS_ENABLED(CONFIG_I2C_IMX)
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&mcf_i2c0,
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#ifdef MCFI2C_BASE1
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&mcf_i2c1,
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#endif
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#ifdef MCFI2C_BASE2
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&mcf_i2c2,
|
|
#endif
|
|
#ifdef MCFI2C_BASE3
|
|
&mcf_i2c3,
|
|
#endif
|
|
#ifdef MCFI2C_BASE4
|
|
&mcf_i2c4,
|
|
#endif
|
|
#ifdef MCFI2C_BASE5
|
|
&mcf_i2c5,
|
|
#endif
|
|
#endif
|
|
};
|
|
|
|
/*
|
|
* Some ColdFire UARTs let you set the IRQ line to use.
|
|
*/
|
|
static void __init mcf_uart_set_irq(void)
|
|
{
|
|
#ifdef MCFUART_UIVR
|
|
/* UART0 interrupt setup */
|
|
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
|
|
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
|
|
mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
|
|
|
|
/* UART1 interrupt setup */
|
|
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
|
|
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
|
|
mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
|
|
#endif
|
|
}
|
|
|
|
static int __init mcf_init_devices(void)
|
|
{
|
|
mcf_uart_set_irq();
|
|
platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
|
|
return 0;
|
|
}
|
|
|
|
arch_initcall(mcf_init_devices);
|
|
|