Eran Ben Elisha f91e6d8941 net/mlx5_core: Add setting ATOMIC endian mode ... HW is capable of 2 requestor endianness modes for standard 8 Bytes atomic: BE (0x0) and host endianness (0x1). Read the supported modes from hca atomic capabilities and configure HW to host endianness mode if supported. Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com> Reviewed-by: Yishai Hadas <yishaih@mellanox.com> Signed-off-by: Doug Ledford <dledford@redhat.com>		2015-12-24 00:17:31 -05:00
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cmd.h	net/mlx5_core: Fix Mellanox copyright note	2015-04-02 16:33:42 -04:00
cq.h	net/mlx5_core: Modify CQ moderation parameters	2015-05-30 18:23:59 -07:00
device.h	IB/mlx5: Add hca_core_clock_offset to udata in init_ucontext	2015-12-23 23:25:59 -05:00
doorbell.h	net/mlx5_core: Fix Mellanox copyright note	2015-04-02 16:33:42 -04:00
driver.h	IB/mlx5: Extend query_device/port to support RoCE	2015-12-23 12:07:37 -05:00
flow_table.h	net/mlx5: Ethernet resource handling files	2015-05-30 18:24:39 -07:00
mlx5_ifc.h	net/mlx5_core: Add setting ATOMIC endian mode	2015-12-24 00:17:31 -05:00
qp.h	IB/mlx5: Add driver cross-channel support	2015-12-23 23:33:14 -05:00
srq.h	net/mlx5_core: Fix Mellanox copyright note	2015-04-02 16:33:42 -04:00
vport.h	net/mlx5_core: Introduce access functions to query vport RoCE fields	2015-12-23 12:07:37 -05:00