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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4089caa7d0
For most OCTEON SoCs there is a repeated and redundant register definition for almost every hardware register, although the register bit fields would not differ from other SoCs. Since the driver code should use only one definition for simplicity, these other fields are just redundant and can be deleted. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org
279 lines
6.3 KiB
C
279 lines
6.3 KiB
C
/***********************license start***************
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* Author: Cavium Inc.
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*
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* Contact: support@cavium.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2014 Cavium Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Inc. for more information
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***********************license end**************************************/
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#ifndef __CVMX_RST_DEFS_H__
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#define __CVMX_RST_DEFS_H__
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#define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull))
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#define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull))
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#define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull))
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#define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8)
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#define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull))
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#define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull))
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#define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull))
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#define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull))
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#define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull))
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#define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull))
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#define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8)
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#define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull))
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union cvmx_rst_boot {
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uint64_t u64;
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struct cvmx_rst_boot_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t chipkill:1;
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uint64_t jtcsrdis:1;
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uint64_t ejtagdis:1;
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uint64_t romen:1;
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uint64_t ckill_ppdis:1;
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uint64_t jt_tstmode:1;
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uint64_t vrm_err:1;
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uint64_t reserved_37_56:20;
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uint64_t c_mul:7;
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uint64_t pnr_mul:6;
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uint64_t reserved_21_23:3;
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uint64_t lboot_oci:3;
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uint64_t lboot_ext:6;
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uint64_t lboot:10;
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uint64_t rboot:1;
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uint64_t rboot_pin:1;
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#else
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uint64_t rboot_pin:1;
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uint64_t rboot:1;
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uint64_t lboot:10;
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uint64_t lboot_ext:6;
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uint64_t lboot_oci:3;
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uint64_t reserved_21_23:3;
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uint64_t pnr_mul:6;
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uint64_t c_mul:7;
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uint64_t reserved_37_56:20;
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uint64_t vrm_err:1;
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uint64_t jt_tstmode:1;
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uint64_t ckill_ppdis:1;
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uint64_t romen:1;
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uint64_t ejtagdis:1;
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uint64_t jtcsrdis:1;
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uint64_t chipkill:1;
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#endif
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} s;
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};
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union cvmx_rst_cfg {
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uint64_t u64;
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struct cvmx_rst_cfg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t bist_delay:58;
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uint64_t reserved_3_5:3;
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uint64_t cntl_clr_bist:1;
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uint64_t warm_clr_bist:1;
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uint64_t soft_clr_bist:1;
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#else
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uint64_t soft_clr_bist:1;
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uint64_t warm_clr_bist:1;
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uint64_t cntl_clr_bist:1;
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uint64_t reserved_3_5:3;
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uint64_t bist_delay:58;
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#endif
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} s;
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};
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union cvmx_rst_ckill {
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uint64_t u64;
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struct cvmx_rst_ckill_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_47_63:17;
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uint64_t timer:47;
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#else
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uint64_t timer:47;
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uint64_t reserved_47_63:17;
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#endif
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} s;
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};
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union cvmx_rst_ctlx {
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uint64_t u64;
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struct cvmx_rst_ctlx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_10_63:54;
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uint64_t prst_link:1;
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uint64_t rst_done:1;
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uint64_t rst_link:1;
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uint64_t host_mode:1;
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uint64_t reserved_4_5:2;
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uint64_t rst_drv:1;
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uint64_t rst_rcv:1;
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uint64_t rst_chip:1;
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uint64_t rst_val:1;
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#else
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uint64_t rst_val:1;
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uint64_t rst_chip:1;
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uint64_t rst_rcv:1;
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uint64_t rst_drv:1;
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uint64_t reserved_4_5:2;
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uint64_t host_mode:1;
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uint64_t rst_link:1;
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uint64_t rst_done:1;
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uint64_t prst_link:1;
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uint64_t reserved_10_63:54;
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#endif
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} s;
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};
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union cvmx_rst_delay {
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uint64_t u64;
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struct cvmx_rst_delay_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t warm_rst_dly:16;
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uint64_t soft_rst_dly:16;
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#else
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uint64_t soft_rst_dly:16;
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uint64_t warm_rst_dly:16;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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};
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union cvmx_rst_eco {
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uint64_t u64;
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struct cvmx_rst_eco_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t eco_rw:32;
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#else
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uint64_t eco_rw:32;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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};
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union cvmx_rst_int {
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uint64_t u64;
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struct cvmx_rst_int_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_12_63:52;
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uint64_t perst:4;
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uint64_t reserved_4_7:4;
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uint64_t rst_link:4;
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#else
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uint64_t rst_link:4;
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uint64_t reserved_4_7:4;
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uint64_t perst:4;
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uint64_t reserved_12_63:52;
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#endif
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} s;
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struct cvmx_rst_int_cn70xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_11_63:53;
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uint64_t perst:3;
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uint64_t reserved_3_7:5;
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uint64_t rst_link:3;
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#else
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uint64_t rst_link:3;
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uint64_t reserved_3_7:5;
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uint64_t perst:3;
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uint64_t reserved_11_63:53;
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#endif
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} cn70xx;
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};
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union cvmx_rst_ocx {
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uint64_t u64;
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struct cvmx_rst_ocx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_3_63:61;
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uint64_t rst_link:3;
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#else
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uint64_t rst_link:3;
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uint64_t reserved_3_63:61;
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#endif
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} s;
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};
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union cvmx_rst_power_dbg {
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uint64_t u64;
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struct cvmx_rst_power_dbg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_3_63:61;
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uint64_t str:3;
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#else
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uint64_t str:3;
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uint64_t reserved_3_63:61;
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#endif
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} s;
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};
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union cvmx_rst_pp_power {
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uint64_t u64;
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struct cvmx_rst_pp_power_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_48_63:16;
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uint64_t gate:48;
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#else
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uint64_t gate:48;
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uint64_t reserved_48_63:16;
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#endif
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} s;
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struct cvmx_rst_pp_power_cn70xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_4_63:60;
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uint64_t gate:4;
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#else
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uint64_t gate:4;
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uint64_t reserved_4_63:60;
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#endif
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} cn70xx;
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};
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union cvmx_rst_soft_prstx {
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uint64_t u64;
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struct cvmx_rst_soft_prstx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_1_63:63;
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uint64_t soft_prst:1;
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#else
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uint64_t soft_prst:1;
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uint64_t reserved_1_63:63;
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#endif
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} s;
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};
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union cvmx_rst_soft_rst {
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uint64_t u64;
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struct cvmx_rst_soft_rst_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_1_63:63;
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uint64_t soft_rst:1;
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#else
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uint64_t soft_rst:1;
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uint64_t reserved_1_63:63;
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#endif
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} s;
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};
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#endif
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