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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4089caa7d0
For most OCTEON SoCs there is a repeated and redundant register definition for almost every hardware register, although the register bit fields would not differ from other SoCs. Since the driver code should use only one definition for simplicity, these other fields are just redundant and can be deleted. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org
102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_DBG_DEFS_H__
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#define __CVMX_DBG_DEFS_H__
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#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull))
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union cvmx_dbg_data {
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uint64_t u64;
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struct cvmx_dbg_data_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_23_63:41;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t reserved_23_63:41;
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#endif
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} s;
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struct cvmx_dbg_data_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_31_63:33;
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uint64_t pll_mul:3;
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uint64_t reserved_23_27:5;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t reserved_23_27:5;
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uint64_t pll_mul:3;
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uint64_t reserved_31_63:33;
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#endif
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} cn30xx;
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struct cvmx_dbg_data_cn38xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t d_mul:4;
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uint64_t dclk_mul2:1;
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uint64_t cclk_div2:1;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t cclk_div2:1;
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uint64_t dclk_mul2:1;
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uint64_t d_mul:4;
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uint64_t reserved_29_63:35;
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#endif
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} cn38xx;
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struct cvmx_dbg_data_cn58xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_29_63:35;
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uint64_t rem:6;
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uint64_t c_mul:5;
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uint64_t dsel_ext:1;
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uint64_t data:17;
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#else
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uint64_t data:17;
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uint64_t dsel_ext:1;
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uint64_t c_mul:5;
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uint64_t rem:6;
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uint64_t reserved_29_63:35;
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#endif
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} cn58xx;
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};
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#endif
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