mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 04:15:27 +07:00
f8b630bc54
Add a handler for reading/writing the guest's view of the ICC_IGRPEN1_EL1 register, which is located in the ICH_VMCR_EL2.VENG1 field. Tested-by: Alexander Graf <agraf@suse.de> Acked-by: David Daney <david.daney@cavium.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@linaro.org>
492 lines
10 KiB
C
492 lines
10 KiB
C
/*
|
|
* Copyright (C) 2012-2015 - ARM Ltd
|
|
* Author: Marc Zyngier <marc.zyngier@arm.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include <linux/compiler.h>
|
|
#include <linux/irqchip/arm-gic-v3.h>
|
|
#include <linux/kvm_host.h>
|
|
|
|
#include <asm/kvm_emulate.h>
|
|
#include <asm/kvm_hyp.h>
|
|
|
|
#define vtr_to_max_lr_idx(v) ((v) & 0xf)
|
|
#define vtr_to_nr_pre_bits(v) ((((u32)(v) >> 26) & 7) + 1)
|
|
|
|
static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
|
|
{
|
|
switch (lr & 0xf) {
|
|
case 0:
|
|
return read_gicreg(ICH_LR0_EL2);
|
|
case 1:
|
|
return read_gicreg(ICH_LR1_EL2);
|
|
case 2:
|
|
return read_gicreg(ICH_LR2_EL2);
|
|
case 3:
|
|
return read_gicreg(ICH_LR3_EL2);
|
|
case 4:
|
|
return read_gicreg(ICH_LR4_EL2);
|
|
case 5:
|
|
return read_gicreg(ICH_LR5_EL2);
|
|
case 6:
|
|
return read_gicreg(ICH_LR6_EL2);
|
|
case 7:
|
|
return read_gicreg(ICH_LR7_EL2);
|
|
case 8:
|
|
return read_gicreg(ICH_LR8_EL2);
|
|
case 9:
|
|
return read_gicreg(ICH_LR9_EL2);
|
|
case 10:
|
|
return read_gicreg(ICH_LR10_EL2);
|
|
case 11:
|
|
return read_gicreg(ICH_LR11_EL2);
|
|
case 12:
|
|
return read_gicreg(ICH_LR12_EL2);
|
|
case 13:
|
|
return read_gicreg(ICH_LR13_EL2);
|
|
case 14:
|
|
return read_gicreg(ICH_LR14_EL2);
|
|
case 15:
|
|
return read_gicreg(ICH_LR15_EL2);
|
|
}
|
|
|
|
unreachable();
|
|
}
|
|
|
|
static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
|
|
{
|
|
switch (lr & 0xf) {
|
|
case 0:
|
|
write_gicreg(val, ICH_LR0_EL2);
|
|
break;
|
|
case 1:
|
|
write_gicreg(val, ICH_LR1_EL2);
|
|
break;
|
|
case 2:
|
|
write_gicreg(val, ICH_LR2_EL2);
|
|
break;
|
|
case 3:
|
|
write_gicreg(val, ICH_LR3_EL2);
|
|
break;
|
|
case 4:
|
|
write_gicreg(val, ICH_LR4_EL2);
|
|
break;
|
|
case 5:
|
|
write_gicreg(val, ICH_LR5_EL2);
|
|
break;
|
|
case 6:
|
|
write_gicreg(val, ICH_LR6_EL2);
|
|
break;
|
|
case 7:
|
|
write_gicreg(val, ICH_LR7_EL2);
|
|
break;
|
|
case 8:
|
|
write_gicreg(val, ICH_LR8_EL2);
|
|
break;
|
|
case 9:
|
|
write_gicreg(val, ICH_LR9_EL2);
|
|
break;
|
|
case 10:
|
|
write_gicreg(val, ICH_LR10_EL2);
|
|
break;
|
|
case 11:
|
|
write_gicreg(val, ICH_LR11_EL2);
|
|
break;
|
|
case 12:
|
|
write_gicreg(val, ICH_LR12_EL2);
|
|
break;
|
|
case 13:
|
|
write_gicreg(val, ICH_LR13_EL2);
|
|
break;
|
|
case 14:
|
|
write_gicreg(val, ICH_LR14_EL2);
|
|
break;
|
|
case 15:
|
|
write_gicreg(val, ICH_LR15_EL2);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void __hyp_text __vgic_v3_write_ap0rn(u32 val, int n)
|
|
{
|
|
switch (n) {
|
|
case 0:
|
|
write_gicreg(val, ICH_AP0R0_EL2);
|
|
break;
|
|
case 1:
|
|
write_gicreg(val, ICH_AP0R1_EL2);
|
|
break;
|
|
case 2:
|
|
write_gicreg(val, ICH_AP0R2_EL2);
|
|
break;
|
|
case 3:
|
|
write_gicreg(val, ICH_AP0R3_EL2);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void __hyp_text __vgic_v3_write_ap1rn(u32 val, int n)
|
|
{
|
|
switch (n) {
|
|
case 0:
|
|
write_gicreg(val, ICH_AP1R0_EL2);
|
|
break;
|
|
case 1:
|
|
write_gicreg(val, ICH_AP1R1_EL2);
|
|
break;
|
|
case 2:
|
|
write_gicreg(val, ICH_AP1R2_EL2);
|
|
break;
|
|
case 3:
|
|
write_gicreg(val, ICH_AP1R3_EL2);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static u32 __hyp_text __vgic_v3_read_ap0rn(int n)
|
|
{
|
|
u32 val;
|
|
|
|
switch (n) {
|
|
case 0:
|
|
val = read_gicreg(ICH_AP0R0_EL2);
|
|
break;
|
|
case 1:
|
|
val = read_gicreg(ICH_AP0R1_EL2);
|
|
break;
|
|
case 2:
|
|
val = read_gicreg(ICH_AP0R2_EL2);
|
|
break;
|
|
case 3:
|
|
val = read_gicreg(ICH_AP0R3_EL2);
|
|
break;
|
|
default:
|
|
unreachable();
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
static u32 __hyp_text __vgic_v3_read_ap1rn(int n)
|
|
{
|
|
u32 val;
|
|
|
|
switch (n) {
|
|
case 0:
|
|
val = read_gicreg(ICH_AP1R0_EL2);
|
|
break;
|
|
case 1:
|
|
val = read_gicreg(ICH_AP1R1_EL2);
|
|
break;
|
|
case 2:
|
|
val = read_gicreg(ICH_AP1R2_EL2);
|
|
break;
|
|
case 3:
|
|
val = read_gicreg(ICH_AP1R3_EL2);
|
|
break;
|
|
default:
|
|
unreachable();
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
|
|
u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
|
|
u64 val;
|
|
|
|
/*
|
|
* Make sure stores to the GIC via the memory mapped interface
|
|
* are now visible to the system register interface.
|
|
*/
|
|
if (!cpu_if->vgic_sre) {
|
|
dsb(st);
|
|
cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
|
|
}
|
|
|
|
if (used_lrs) {
|
|
int i;
|
|
u32 nr_pre_bits;
|
|
|
|
cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
|
|
|
|
write_gicreg(0, ICH_HCR_EL2);
|
|
val = read_gicreg(ICH_VTR_EL2);
|
|
nr_pre_bits = vtr_to_nr_pre_bits(val);
|
|
|
|
for (i = 0; i < used_lrs; i++) {
|
|
if (cpu_if->vgic_elrsr & (1 << i))
|
|
cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
|
|
else
|
|
cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
|
|
|
|
__gic_v3_set_lr(0, i);
|
|
}
|
|
|
|
switch (nr_pre_bits) {
|
|
case 7:
|
|
cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3);
|
|
cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);
|
|
case 6:
|
|
cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);
|
|
default:
|
|
cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0);
|
|
}
|
|
|
|
switch (nr_pre_bits) {
|
|
case 7:
|
|
cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3);
|
|
cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);
|
|
case 6:
|
|
cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);
|
|
default:
|
|
cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);
|
|
}
|
|
} else {
|
|
cpu_if->vgic_elrsr = 0xffff;
|
|
cpu_if->vgic_ap0r[0] = 0;
|
|
cpu_if->vgic_ap0r[1] = 0;
|
|
cpu_if->vgic_ap0r[2] = 0;
|
|
cpu_if->vgic_ap0r[3] = 0;
|
|
cpu_if->vgic_ap1r[0] = 0;
|
|
cpu_if->vgic_ap1r[1] = 0;
|
|
cpu_if->vgic_ap1r[2] = 0;
|
|
cpu_if->vgic_ap1r[3] = 0;
|
|
}
|
|
|
|
val = read_gicreg(ICC_SRE_EL2);
|
|
write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
|
|
|
|
if (!cpu_if->vgic_sre) {
|
|
/* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
|
|
isb();
|
|
write_gicreg(1, ICC_SRE_EL1);
|
|
}
|
|
}
|
|
|
|
void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
|
|
u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs;
|
|
u64 val;
|
|
u32 nr_pre_bits;
|
|
int i;
|
|
|
|
/*
|
|
* VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
|
|
* Group0 interrupt (as generated in GICv2 mode) to be
|
|
* delivered as a FIQ to the guest, with potentially fatal
|
|
* consequences. So we must make sure that ICC_SRE_EL1 has
|
|
* been actually programmed with the value we want before
|
|
* starting to mess with the rest of the GIC, and VMCR_EL2 in
|
|
* particular.
|
|
*/
|
|
if (!cpu_if->vgic_sre) {
|
|
write_gicreg(0, ICC_SRE_EL1);
|
|
isb();
|
|
write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
|
|
}
|
|
|
|
val = read_gicreg(ICH_VTR_EL2);
|
|
nr_pre_bits = vtr_to_nr_pre_bits(val);
|
|
|
|
if (used_lrs) {
|
|
write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
|
|
|
|
switch (nr_pre_bits) {
|
|
case 7:
|
|
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3);
|
|
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2);
|
|
case 6:
|
|
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1);
|
|
default:
|
|
__vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0);
|
|
}
|
|
|
|
switch (nr_pre_bits) {
|
|
case 7:
|
|
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3);
|
|
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2);
|
|
case 6:
|
|
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1);
|
|
default:
|
|
__vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0);
|
|
}
|
|
|
|
for (i = 0; i < used_lrs; i++)
|
|
__gic_v3_set_lr(cpu_if->vgic_lr[i], i);
|
|
}
|
|
|
|
/*
|
|
* Ensures that the above will have reached the
|
|
* (re)distributors. This ensure the guest will read the
|
|
* correct values from the memory-mapped interface.
|
|
*/
|
|
if (!cpu_if->vgic_sre) {
|
|
isb();
|
|
dsb(sy);
|
|
}
|
|
|
|
/*
|
|
* Prevent the guest from touching the GIC system registers if
|
|
* SRE isn't enabled for GICv3 emulation.
|
|
*/
|
|
write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
|
|
ICC_SRE_EL2);
|
|
}
|
|
|
|
void __hyp_text __vgic_v3_init_lrs(void)
|
|
{
|
|
int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
|
|
int i;
|
|
|
|
for (i = 0; i <= max_lr_idx; i++)
|
|
__gic_v3_set_lr(0, i);
|
|
}
|
|
|
|
u64 __hyp_text __vgic_v3_get_ich_vtr_el2(void)
|
|
{
|
|
return read_gicreg(ICH_VTR_EL2);
|
|
}
|
|
|
|
u64 __hyp_text __vgic_v3_read_vmcr(void)
|
|
{
|
|
return read_gicreg(ICH_VMCR_EL2);
|
|
}
|
|
|
|
void __hyp_text __vgic_v3_write_vmcr(u32 vmcr)
|
|
{
|
|
write_gicreg(vmcr, ICH_VMCR_EL2);
|
|
}
|
|
|
|
#ifdef CONFIG_ARM64
|
|
|
|
static int __hyp_text __vgic_v3_bpr_min(void)
|
|
{
|
|
/* See Pseudocode for VPriorityGroup */
|
|
return 8 - vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2));
|
|
}
|
|
|
|
static unsigned int __hyp_text __vgic_v3_get_bpr0(u32 vmcr)
|
|
{
|
|
return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
|
|
}
|
|
|
|
static unsigned int __hyp_text __vgic_v3_get_bpr1(u32 vmcr)
|
|
{
|
|
unsigned int bpr;
|
|
|
|
if (vmcr & ICH_VMCR_CBPR_MASK) {
|
|
bpr = __vgic_v3_get_bpr0(vmcr);
|
|
if (bpr < 7)
|
|
bpr++;
|
|
} else {
|
|
bpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
|
|
}
|
|
|
|
return bpr;
|
|
}
|
|
|
|
static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
|
|
{
|
|
vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
|
|
}
|
|
|
|
static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
|
|
{
|
|
u64 val = vcpu_get_reg(vcpu, rt);
|
|
|
|
if (val & 1)
|
|
vmcr |= ICH_VMCR_ENG1_MASK;
|
|
else
|
|
vmcr &= ~ICH_VMCR_ENG1_MASK;
|
|
|
|
__vgic_v3_write_vmcr(vmcr);
|
|
}
|
|
|
|
static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
|
|
{
|
|
vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
|
|
}
|
|
|
|
static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
|
|
{
|
|
u64 val = vcpu_get_reg(vcpu, rt);
|
|
u8 bpr_min = __vgic_v3_bpr_min();
|
|
|
|
if (vmcr & ICH_VMCR_CBPR_MASK)
|
|
return;
|
|
|
|
/* Enforce BPR limiting */
|
|
if (val < bpr_min)
|
|
val = bpr_min;
|
|
|
|
val <<= ICH_VMCR_BPR1_SHIFT;
|
|
val &= ICH_VMCR_BPR1_MASK;
|
|
vmcr &= ~ICH_VMCR_BPR1_MASK;
|
|
vmcr |= val;
|
|
|
|
__vgic_v3_write_vmcr(vmcr);
|
|
}
|
|
|
|
int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
|
|
{
|
|
int rt;
|
|
u32 esr;
|
|
u32 vmcr;
|
|
void (*fn)(struct kvm_vcpu *, u32, int);
|
|
bool is_read;
|
|
u32 sysreg;
|
|
|
|
esr = kvm_vcpu_get_hsr(vcpu);
|
|
if (vcpu_mode_is_32bit(vcpu)) {
|
|
if (!kvm_condition_valid(vcpu))
|
|
return 1;
|
|
|
|
sysreg = esr_cp15_to_sysreg(esr);
|
|
} else {
|
|
sysreg = esr_sys64_to_sysreg(esr);
|
|
}
|
|
|
|
is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
|
|
|
|
switch (sysreg) {
|
|
case SYS_ICC_GRPEN1_EL1:
|
|
if (is_read)
|
|
fn = __vgic_v3_read_igrpen1;
|
|
else
|
|
fn = __vgic_v3_write_igrpen1;
|
|
break;
|
|
case SYS_ICC_BPR1_EL1:
|
|
if (is_read)
|
|
fn = __vgic_v3_read_bpr1;
|
|
else
|
|
fn = __vgic_v3_write_bpr1;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
vmcr = __vgic_v3_read_vmcr();
|
|
rt = kvm_vcpu_sys_get_rt(vcpu);
|
|
fn(vcpu, vmcr, rt);
|
|
|
|
return 1;
|
|
}
|
|
|
|
#endif
|