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f81dadbcf7
There are two chip pins named TXDLY and RXDLY which actually adds the 2ns
delays to TXC and RXC for TXD/RXD latching. Alas this is the only
documented info regarding the RGMII timing control configurations the PHY
provides. It turns out the same settings can be setup via MDIO registers
hidden in the extension pages layout. Particularly the extension page 0xa4
provides a register 0x1c, which bits 1 and 2 control the described delays.
They are used to implement the "rgmii-{id,rxid,txid}" phy-mode.
The hidden RGMII configs register utilization was found in the rtl8211e
U-boot driver:
https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99
There is also a freebsd-folks discussion regarding this register:
https://reviews.freebsd.org/D13591
It confirms that the register bits field must control the so called
configuration pins described in the table 12-13 of the official PHY
datasheet:
8:6 = PHY Address
5:4 = Auto-Negotiation
3 = Interface Mode Select
2 = RX Delay
1 = TX Delay
0 = SELRGV
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
338 lines
8.3 KiB
C
338 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* drivers/net/phy/realtek.c
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*
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* Driver for Realtek PHYs
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*
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* Author: Johnson Leung <r58129@freescale.com>
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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#define RTL821x_PHYSR 0x11
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#define RTL821x_PHYSR_DUPLEX BIT(13)
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#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
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#define RTL821x_INER 0x12
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#define RTL8211B_INER_INIT 0x6400
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#define RTL8211E_INER_LINK_STATUS BIT(10)
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#define RTL8211F_INER_LINK_STATUS BIT(4)
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#define RTL821x_INSR 0x13
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#define RTL821x_EXT_PAGE_SELECT 0x1e
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#define RTL821x_PAGE_SELECT 0x1f
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#define RTL8211F_INSR 0x1d
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#define RTL8211F_TX_DELAY BIT(8)
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#define RTL8211E_TX_DELAY BIT(1)
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#define RTL8211E_RX_DELAY BIT(2)
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#define RTL8211E_MODE_MII_GMII BIT(3)
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#define RTL8201F_ISR 0x1e
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#define RTL8201F_IER 0x13
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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MODULE_DESCRIPTION("Realtek PHY driver");
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MODULE_AUTHOR("Johnson Leung");
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MODULE_LICENSE("GPL");
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static int rtl821x_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, RTL821x_PAGE_SELECT);
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}
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static int rtl821x_write_page(struct phy_device *phydev, int page)
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{
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return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
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}
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static int rtl8201_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, RTL8201F_ISR);
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return (err < 0) ? err : 0;
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}
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static int rtl821x_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, RTL821x_INSR);
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return (err < 0) ? err : 0;
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}
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static int rtl8211f_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
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return (err < 0) ? err : 0;
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}
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static int rtl8201_config_intr(struct phy_device *phydev)
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{
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u16 val;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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val = BIT(13) | BIT(12) | BIT(11);
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else
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val = 0;
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return phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
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}
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static int rtl8211b_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, RTL821x_INER,
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RTL8211B_INER_INIT);
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else
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err = phy_write(phydev, RTL821x_INER, 0);
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return err;
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}
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static int rtl8211e_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, RTL821x_INER,
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RTL8211E_INER_LINK_STATUS);
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else
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err = phy_write(phydev, RTL821x_INER, 0);
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return err;
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}
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static int rtl8211f_config_intr(struct phy_device *phydev)
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{
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u16 val;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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val = RTL8211F_INER_LINK_STATUS;
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else
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val = 0;
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return phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
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}
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static int rtl8211_config_aneg(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_config_aneg(phydev);
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if (ret < 0)
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return ret;
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/* Quirk was copied from vendor driver. Unfortunately it includes no
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* description of the magic numbers.
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*/
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if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
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phy_write(phydev, 0x17, 0x2138);
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phy_write(phydev, 0x0e, 0x0260);
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} else {
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phy_write(phydev, 0x17, 0x2108);
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phy_write(phydev, 0x0e, 0x0000);
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}
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return 0;
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}
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static int rtl8211c_config_init(struct phy_device *phydev)
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{
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/* RTL8211C has an issue when operating in Gigabit slave mode */
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return phy_set_bits(phydev, MII_CTRL1000,
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CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
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}
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static int rtl8211f_config_init(struct phy_device *phydev)
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{
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u16 val = 0;
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/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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val = RTL8211F_TX_DELAY;
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return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val);
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}
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static int rtl8211e_config_init(struct phy_device *phydev)
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{
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int ret = 0, oldpage;
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u16 val;
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/* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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val = 0;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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val = RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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val = RTL8211E_RX_DELAY;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val = RTL8211E_TX_DELAY;
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break;
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default: /* the rest of the modes imply leaving delays as is. */
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return 0;
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}
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/* According to a sample driver there is a 0x1c config register on the
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* 0xa4 extension page (0x7) layout. It can be used to disable/enable
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* the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. It can
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* also be used to customize the whole configuration register:
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* 8:6 = PHY Address, 5:4 = Auto-Negotiation, 3 = Interface Mode Select,
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* 2 = RX Delay, 1 = TX Delay, 0 = SELRGV (see original PHY datasheet
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* for details).
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*/
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oldpage = phy_select_page(phydev, 0x7);
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if (oldpage < 0)
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goto err_restore_page;
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ret = phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
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if (ret)
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goto err_restore_page;
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ret = phy_modify(phydev, 0x1c, RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
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val);
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err_restore_page:
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return phy_restore_page(phydev, oldpage, ret);
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}
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static int rtl8211b_suspend(struct phy_device *phydev)
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{
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phy_write(phydev, MII_MMD_DATA, BIT(9));
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return genphy_suspend(phydev);
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}
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static int rtl8211b_resume(struct phy_device *phydev)
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{
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phy_write(phydev, MII_MMD_DATA, 0);
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return genphy_resume(phydev);
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}
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static int rtl8366rb_config_init(struct phy_device *phydev)
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{
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int ret;
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ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
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RTL8366RB_POWER_SAVE_ON);
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if (ret) {
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dev_err(&phydev->mdio.dev,
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"error enabling power management\n");
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}
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return ret;
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}
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static struct phy_driver realtek_drvs[] = {
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{
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PHY_ID_MATCH_EXACT(0x00008201),
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.name = "RTL8201CP Ethernet",
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}, {
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PHY_ID_MATCH_EXACT(0x001cc816),
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.name = "RTL8201F Fast Ethernet",
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.ack_interrupt = &rtl8201_ack_interrupt,
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.config_intr = &rtl8201_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc910),
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.name = "RTL8211 Gigabit Ethernet",
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.config_aneg = rtl8211_config_aneg,
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.read_mmd = &genphy_read_mmd_unsupported,
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.write_mmd = &genphy_write_mmd_unsupported,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc912),
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.name = "RTL8211B Gigabit Ethernet",
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.ack_interrupt = &rtl821x_ack_interrupt,
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.config_intr = &rtl8211b_config_intr,
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.read_mmd = &genphy_read_mmd_unsupported,
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.write_mmd = &genphy_write_mmd_unsupported,
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.suspend = rtl8211b_suspend,
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.resume = rtl8211b_resume,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc913),
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.name = "RTL8211C Gigabit Ethernet",
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.config_init = rtl8211c_config_init,
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.read_mmd = &genphy_read_mmd_unsupported,
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.write_mmd = &genphy_write_mmd_unsupported,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc914),
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.name = "RTL8211DN Gigabit Ethernet",
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.ack_interrupt = rtl821x_ack_interrupt,
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.config_intr = rtl8211e_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc915),
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.name = "RTL8211E Gigabit Ethernet",
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.config_init = &rtl8211e_config_init,
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.ack_interrupt = &rtl821x_ack_interrupt,
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.config_intr = &rtl8211e_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc916),
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.name = "RTL8211F Gigabit Ethernet",
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.config_init = &rtl8211f_config_init,
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.ack_interrupt = &rtl8211f_ack_interrupt,
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.config_intr = &rtl8211f_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc800),
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.name = "Generic Realtek PHY",
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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}, {
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PHY_ID_MATCH_EXACT(0x001cc961),
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.name = "RTL8366RB Gigabit Ethernet",
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.config_init = &rtl8366rb_config_init,
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/* These interrupts are handled by the irq controller
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* embedded inside the RTL8366RB, they get unmasked when the
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* irq is requested and ACKed by reading the status register,
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* which is done by the irqchip code.
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*/
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.ack_interrupt = genphy_no_ack_interrupt,
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.config_intr = genphy_no_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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};
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module_phy_driver(realtek_drvs);
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static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
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{ PHY_ID_MATCH_VENDOR(0x001cc800) },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, realtek_tbl);
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