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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cd70387f89
Old pinctrl drivers will need to disable strict mode for various reasons,
among which:
- Some DT will still have a pinctrl group for each GPIO used, which will
be rejected by pin_request. While we could remove those nodes, we still
have to deal with old DTs.
- Some GPIOs on these boards need to have their pin configuration changed
(for bias or current), and there's no clear migration path
Let's disable the strict mode on those SoCs so that there's no breakage.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
149 lines
4.7 KiB
C
149 lines
4.7 KiB
C
/*
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* Allwinner A31 SoCs special pins pinctrl driver.
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*
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* Copyright (C) 2014 Boris Brezillon
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* Boris Brezillon <boris.brezillon@free-electrons.com>
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*
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* Copyright (C) 2014 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/reset.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
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SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
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SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */
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SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */
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SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */
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SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */
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SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */
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SUNXI_FUNCTION(0x3, "1wire")),
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */
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SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
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};
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static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
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.pins = sun6i_a31_r_pins,
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.npins = ARRAY_SIZE(sun6i_a31_r_pins),
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.pin_base = PL_BASE,
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.irq_banks = 2,
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.disable_strict_mode = true,
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};
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static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
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{
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struct reset_control *rstc;
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int ret;
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rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(rstc)) {
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dev_err(&pdev->dev, "Reset controller missing\n");
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return PTR_ERR(rstc);
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}
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ret = reset_control_deassert(rstc);
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if (ret)
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return ret;
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ret = sunxi_pinctrl_init(pdev,
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&sun6i_a31_r_pinctrl_data);
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if (ret)
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reset_control_assert(rstc);
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return ret;
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}
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static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {
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{ .compatible = "allwinner,sun6i-a31-r-pinctrl", },
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{}
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};
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static struct platform_driver sun6i_a31_r_pinctrl_driver = {
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.probe = sun6i_a31_r_pinctrl_probe,
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.driver = {
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.name = "sun6i-a31-r-pinctrl",
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.of_match_table = sun6i_a31_r_pinctrl_match,
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},
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};
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builtin_platform_driver(sun6i_a31_r_pinctrl_driver);
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