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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a45ff5994c
- Add support for chained PMU counters in guests - Improve SError handling - Handle Neoverse N1 erratum #1349291 - Allow side-channel mitigation status to be migrated - Standardise most AArch64 system register accesses to msr_s/mrs_s - Fix host MPIDR corruption on 32bit -----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl0kge4VHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDYyQP/3XY5tFcLKkp/h9rnGaCXwAxhNzn TyF/IZEFBKFTSoDMXKLLc8KllvoPQ7aUl03heYbuayYpyKR1+LCx7lDwu1MYyEf+ aSSuOKlbG//tLUEGp09pTRCgjs2mhhZYqOj5GF2mZ7xpovFVSNOPzTazbXDNQ7tw zUAs43YNg+bUMwj+SLWpBlizjrLr7T34utIr6daKJE/GSfmIrcYXhGbZqUh0zbO0 z5LNasebws8/pHyeGI7+/yoMIKaQ8foMgywTpsRpBsx6YI+AbOLjEmCk2IBOPcEK pm9KkSIBZEO2CSxZKl3NQiEow/Qd/lnz2xLMCSfh4XrYoI2Th4gNcsbJpiBDWP5a 0eZ5jSiexxKngIbM+to7jR3m0yc9RgcuzceJg3Uly7Ya0vb5RqKwOX4Ge4XP4VDT DzIVFdQjxDKdVIf3EvGp1cj4P7dRUU3xbZcbzyuRPEmT3vgjEnbxawmPLs3QMAl1 31Wd2wIsPB86kSxzSMel27Vs5VgMhgyHE26zN91R745CvhDXaDKydIWjGjdVMHsB GuX/h2kL+ohx+N/OpZPgwsVUAGLSOQFP3pE/EcGtqc2kkfqa+bx12DKcZ3zdmJvy +cu5ixU8q5thPH/pZob/C3hKUY/eLy02emS34RK0Jh2sZHbQgAOtMsiqUxNHEjUm 6TkpdWa5SRd7CtGV =yfCs -----END PGP SIGNATURE----- Merge tag 'kvm-arm-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm updates for 5.3 - Add support for chained PMU counters in guests - Improve SError handling - Handle Neoverse N1 erratum #1349291 - Allow side-channel mitigation status to be migrated - Standardise most AArch64 system register accesses to msr_s/mrs_s - Fix host MPIDR corruption on 32bit
443 lines
14 KiB
C
443 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_VMCS12_H
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#define __KVM_X86_VMX_VMCS12_H
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#include <linux/build_bug.h>
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#include "vmcs.h"
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/*
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* struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
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* single nested guest (L2), hence the name vmcs12. Any VMX implementation has
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* a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
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* stored in guest memory specified by VMPTRLD, but is opaque to the guest,
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* which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
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* More than one of these structures may exist, if L1 runs multiple L2 guests.
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* nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
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* underlying hardware which will be used to run L2.
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* This structure is packed to ensure that its layout is identical across
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* machines (necessary for live migration).
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*
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* IMPORTANT: Changing the layout of existing fields in this structure
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* will break save/restore compatibility with older kvm releases. When
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* adding new fields, either use space in the reserved padding* arrays
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* or add the new fields to the end of the structure.
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*/
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typedef u64 natural_width;
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struct __packed vmcs12 {
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/* According to the Intel spec, a VMCS region must start with the
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* following two fields. Then follow implementation-specific data.
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*/
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struct vmcs_hdr hdr;
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u32 abort;
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u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
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u32 padding[7]; /* room for future expansion */
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u64 io_bitmap_a;
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u64 io_bitmap_b;
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u64 msr_bitmap;
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u64 vm_exit_msr_store_addr;
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u64 vm_exit_msr_load_addr;
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u64 vm_entry_msr_load_addr;
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u64 tsc_offset;
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u64 virtual_apic_page_addr;
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u64 apic_access_addr;
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u64 posted_intr_desc_addr;
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u64 ept_pointer;
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u64 eoi_exit_bitmap0;
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u64 eoi_exit_bitmap1;
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u64 eoi_exit_bitmap2;
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u64 eoi_exit_bitmap3;
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u64 xss_exit_bitmap;
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u64 guest_physical_address;
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u64 vmcs_link_pointer;
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u64 guest_ia32_debugctl;
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u64 guest_ia32_pat;
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u64 guest_ia32_efer;
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u64 guest_ia32_perf_global_ctrl;
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u64 guest_pdptr0;
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u64 guest_pdptr1;
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u64 guest_pdptr2;
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u64 guest_pdptr3;
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u64 guest_bndcfgs;
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u64 host_ia32_pat;
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u64 host_ia32_efer;
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u64 host_ia32_perf_global_ctrl;
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u64 vmread_bitmap;
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u64 vmwrite_bitmap;
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u64 vm_function_control;
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u64 eptp_list_address;
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u64 pml_address;
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u64 padding64[3]; /* room for future expansion */
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/*
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* To allow migration of L1 (complete with its L2 guests) between
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* machines of different natural widths (32 or 64 bit), we cannot have
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* unsigned long fields with no explicit size. We use u64 (aliased
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* natural_width) instead. Luckily, x86 is little-endian.
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*/
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natural_width cr0_guest_host_mask;
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natural_width cr4_guest_host_mask;
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natural_width cr0_read_shadow;
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natural_width cr4_read_shadow;
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natural_width cr3_target_value0;
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natural_width cr3_target_value1;
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natural_width cr3_target_value2;
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natural_width cr3_target_value3;
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natural_width exit_qualification;
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natural_width guest_linear_address;
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natural_width guest_cr0;
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natural_width guest_cr3;
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natural_width guest_cr4;
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natural_width guest_es_base;
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natural_width guest_cs_base;
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natural_width guest_ss_base;
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natural_width guest_ds_base;
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natural_width guest_fs_base;
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natural_width guest_gs_base;
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natural_width guest_ldtr_base;
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natural_width guest_tr_base;
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natural_width guest_gdtr_base;
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natural_width guest_idtr_base;
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natural_width guest_dr7;
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natural_width guest_rsp;
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natural_width guest_rip;
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natural_width guest_rflags;
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natural_width guest_pending_dbg_exceptions;
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natural_width guest_sysenter_esp;
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natural_width guest_sysenter_eip;
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natural_width host_cr0;
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natural_width host_cr3;
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natural_width host_cr4;
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natural_width host_fs_base;
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natural_width host_gs_base;
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natural_width host_tr_base;
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natural_width host_gdtr_base;
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natural_width host_idtr_base;
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natural_width host_ia32_sysenter_esp;
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natural_width host_ia32_sysenter_eip;
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natural_width host_rsp;
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natural_width host_rip;
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natural_width paddingl[8]; /* room for future expansion */
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u32 pin_based_vm_exec_control;
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u32 cpu_based_vm_exec_control;
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u32 exception_bitmap;
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u32 page_fault_error_code_mask;
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u32 page_fault_error_code_match;
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u32 cr3_target_count;
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u32 vm_exit_controls;
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u32 vm_exit_msr_store_count;
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u32 vm_exit_msr_load_count;
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u32 vm_entry_controls;
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u32 vm_entry_msr_load_count;
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u32 vm_entry_intr_info_field;
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u32 vm_entry_exception_error_code;
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u32 vm_entry_instruction_len;
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u32 tpr_threshold;
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u32 secondary_vm_exec_control;
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u32 vm_instruction_error;
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u32 vm_exit_reason;
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u32 vm_exit_intr_info;
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u32 vm_exit_intr_error_code;
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u32 idt_vectoring_info_field;
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u32 idt_vectoring_error_code;
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u32 vm_exit_instruction_len;
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u32 vmx_instruction_info;
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u32 guest_es_limit;
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u32 guest_cs_limit;
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u32 guest_ss_limit;
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u32 guest_ds_limit;
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u32 guest_fs_limit;
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u32 guest_gs_limit;
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u32 guest_ldtr_limit;
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u32 guest_tr_limit;
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u32 guest_gdtr_limit;
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u32 guest_idtr_limit;
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u32 guest_es_ar_bytes;
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u32 guest_cs_ar_bytes;
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u32 guest_ss_ar_bytes;
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u32 guest_ds_ar_bytes;
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u32 guest_fs_ar_bytes;
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u32 guest_gs_ar_bytes;
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u32 guest_ldtr_ar_bytes;
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u32 guest_tr_ar_bytes;
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u32 guest_interruptibility_info;
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u32 guest_activity_state;
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u32 guest_sysenter_cs;
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u32 host_ia32_sysenter_cs;
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u32 vmx_preemption_timer_value;
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u32 padding32[7]; /* room for future expansion */
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u16 virtual_processor_id;
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u16 posted_intr_nv;
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u16 guest_es_selector;
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u16 guest_cs_selector;
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u16 guest_ss_selector;
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u16 guest_ds_selector;
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u16 guest_fs_selector;
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u16 guest_gs_selector;
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u16 guest_ldtr_selector;
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u16 guest_tr_selector;
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u16 guest_intr_status;
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u16 host_es_selector;
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u16 host_cs_selector;
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u16 host_ss_selector;
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u16 host_ds_selector;
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u16 host_fs_selector;
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u16 host_gs_selector;
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u16 host_tr_selector;
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u16 guest_pml_index;
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};
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/*
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* VMCS12_REVISION is an arbitrary id that should be changed if the content or
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* layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
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* VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
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*
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* IMPORTANT: Changing this value will break save/restore compatibility with
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* older kvm releases.
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*/
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#define VMCS12_REVISION 0x11e57ed0
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/*
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* VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
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* and any VMCS region. Although only sizeof(struct vmcs12) are used by the
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* current implementation, 4K are reserved to avoid future complications and
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* to preserve userspace ABI.
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*/
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#define VMCS12_SIZE KVM_STATE_NESTED_VMX_VMCS_SIZE
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/*
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* VMCS12_MAX_FIELD_INDEX is the highest index value used in any
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* supported VMCS12 field encoding.
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*/
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#define VMCS12_MAX_FIELD_INDEX 0x17
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/*
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* For save/restore compatibility, the vmcs12 field offsets must not change.
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*/
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#define CHECK_OFFSET(field, loc) \
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BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc), \
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"Offset of " #field " in struct vmcs12 has changed.")
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static inline void vmx_check_vmcs12_offsets(void)
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{
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CHECK_OFFSET(hdr, 0);
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CHECK_OFFSET(abort, 4);
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CHECK_OFFSET(launch_state, 8);
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CHECK_OFFSET(io_bitmap_a, 40);
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CHECK_OFFSET(io_bitmap_b, 48);
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CHECK_OFFSET(msr_bitmap, 56);
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CHECK_OFFSET(vm_exit_msr_store_addr, 64);
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CHECK_OFFSET(vm_exit_msr_load_addr, 72);
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CHECK_OFFSET(vm_entry_msr_load_addr, 80);
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CHECK_OFFSET(tsc_offset, 88);
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CHECK_OFFSET(virtual_apic_page_addr, 96);
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CHECK_OFFSET(apic_access_addr, 104);
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CHECK_OFFSET(posted_intr_desc_addr, 112);
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CHECK_OFFSET(ept_pointer, 120);
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CHECK_OFFSET(eoi_exit_bitmap0, 128);
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CHECK_OFFSET(eoi_exit_bitmap1, 136);
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CHECK_OFFSET(eoi_exit_bitmap2, 144);
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CHECK_OFFSET(eoi_exit_bitmap3, 152);
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CHECK_OFFSET(xss_exit_bitmap, 160);
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CHECK_OFFSET(guest_physical_address, 168);
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CHECK_OFFSET(vmcs_link_pointer, 176);
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CHECK_OFFSET(guest_ia32_debugctl, 184);
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CHECK_OFFSET(guest_ia32_pat, 192);
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CHECK_OFFSET(guest_ia32_efer, 200);
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CHECK_OFFSET(guest_ia32_perf_global_ctrl, 208);
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CHECK_OFFSET(guest_pdptr0, 216);
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CHECK_OFFSET(guest_pdptr1, 224);
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CHECK_OFFSET(guest_pdptr2, 232);
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CHECK_OFFSET(guest_pdptr3, 240);
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CHECK_OFFSET(guest_bndcfgs, 248);
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CHECK_OFFSET(host_ia32_pat, 256);
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CHECK_OFFSET(host_ia32_efer, 264);
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CHECK_OFFSET(host_ia32_perf_global_ctrl, 272);
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CHECK_OFFSET(vmread_bitmap, 280);
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CHECK_OFFSET(vmwrite_bitmap, 288);
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CHECK_OFFSET(vm_function_control, 296);
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CHECK_OFFSET(eptp_list_address, 304);
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CHECK_OFFSET(pml_address, 312);
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CHECK_OFFSET(cr0_guest_host_mask, 344);
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CHECK_OFFSET(cr4_guest_host_mask, 352);
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CHECK_OFFSET(cr0_read_shadow, 360);
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CHECK_OFFSET(cr4_read_shadow, 368);
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CHECK_OFFSET(cr3_target_value0, 376);
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CHECK_OFFSET(cr3_target_value1, 384);
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CHECK_OFFSET(cr3_target_value2, 392);
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CHECK_OFFSET(cr3_target_value3, 400);
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CHECK_OFFSET(exit_qualification, 408);
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CHECK_OFFSET(guest_linear_address, 416);
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CHECK_OFFSET(guest_cr0, 424);
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CHECK_OFFSET(guest_cr3, 432);
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CHECK_OFFSET(guest_cr4, 440);
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CHECK_OFFSET(guest_es_base, 448);
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CHECK_OFFSET(guest_cs_base, 456);
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CHECK_OFFSET(guest_ss_base, 464);
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CHECK_OFFSET(guest_ds_base, 472);
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CHECK_OFFSET(guest_fs_base, 480);
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CHECK_OFFSET(guest_gs_base, 488);
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CHECK_OFFSET(guest_ldtr_base, 496);
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CHECK_OFFSET(guest_tr_base, 504);
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CHECK_OFFSET(guest_gdtr_base, 512);
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CHECK_OFFSET(guest_idtr_base, 520);
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CHECK_OFFSET(guest_dr7, 528);
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CHECK_OFFSET(guest_rsp, 536);
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CHECK_OFFSET(guest_rip, 544);
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CHECK_OFFSET(guest_rflags, 552);
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CHECK_OFFSET(guest_pending_dbg_exceptions, 560);
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CHECK_OFFSET(guest_sysenter_esp, 568);
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CHECK_OFFSET(guest_sysenter_eip, 576);
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CHECK_OFFSET(host_cr0, 584);
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CHECK_OFFSET(host_cr3, 592);
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CHECK_OFFSET(host_cr4, 600);
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CHECK_OFFSET(host_fs_base, 608);
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CHECK_OFFSET(host_gs_base, 616);
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CHECK_OFFSET(host_tr_base, 624);
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CHECK_OFFSET(host_gdtr_base, 632);
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CHECK_OFFSET(host_idtr_base, 640);
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CHECK_OFFSET(host_ia32_sysenter_esp, 648);
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CHECK_OFFSET(host_ia32_sysenter_eip, 656);
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CHECK_OFFSET(host_rsp, 664);
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CHECK_OFFSET(host_rip, 672);
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CHECK_OFFSET(pin_based_vm_exec_control, 744);
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CHECK_OFFSET(cpu_based_vm_exec_control, 748);
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CHECK_OFFSET(exception_bitmap, 752);
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CHECK_OFFSET(page_fault_error_code_mask, 756);
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CHECK_OFFSET(page_fault_error_code_match, 760);
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CHECK_OFFSET(cr3_target_count, 764);
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CHECK_OFFSET(vm_exit_controls, 768);
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CHECK_OFFSET(vm_exit_msr_store_count, 772);
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CHECK_OFFSET(vm_exit_msr_load_count, 776);
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CHECK_OFFSET(vm_entry_controls, 780);
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CHECK_OFFSET(vm_entry_msr_load_count, 784);
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CHECK_OFFSET(vm_entry_intr_info_field, 788);
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CHECK_OFFSET(vm_entry_exception_error_code, 792);
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CHECK_OFFSET(vm_entry_instruction_len, 796);
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CHECK_OFFSET(tpr_threshold, 800);
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CHECK_OFFSET(secondary_vm_exec_control, 804);
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CHECK_OFFSET(vm_instruction_error, 808);
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CHECK_OFFSET(vm_exit_reason, 812);
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CHECK_OFFSET(vm_exit_intr_info, 816);
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CHECK_OFFSET(vm_exit_intr_error_code, 820);
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CHECK_OFFSET(idt_vectoring_info_field, 824);
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CHECK_OFFSET(idt_vectoring_error_code, 828);
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CHECK_OFFSET(vm_exit_instruction_len, 832);
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CHECK_OFFSET(vmx_instruction_info, 836);
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CHECK_OFFSET(guest_es_limit, 840);
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CHECK_OFFSET(guest_cs_limit, 844);
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CHECK_OFFSET(guest_ss_limit, 848);
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CHECK_OFFSET(guest_ds_limit, 852);
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CHECK_OFFSET(guest_fs_limit, 856);
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CHECK_OFFSET(guest_gs_limit, 860);
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CHECK_OFFSET(guest_ldtr_limit, 864);
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CHECK_OFFSET(guest_tr_limit, 868);
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CHECK_OFFSET(guest_gdtr_limit, 872);
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CHECK_OFFSET(guest_idtr_limit, 876);
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CHECK_OFFSET(guest_es_ar_bytes, 880);
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CHECK_OFFSET(guest_cs_ar_bytes, 884);
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CHECK_OFFSET(guest_ss_ar_bytes, 888);
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CHECK_OFFSET(guest_ds_ar_bytes, 892);
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CHECK_OFFSET(guest_fs_ar_bytes, 896);
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CHECK_OFFSET(guest_gs_ar_bytes, 900);
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CHECK_OFFSET(guest_ldtr_ar_bytes, 904);
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CHECK_OFFSET(guest_tr_ar_bytes, 908);
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CHECK_OFFSET(guest_interruptibility_info, 912);
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CHECK_OFFSET(guest_activity_state, 916);
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CHECK_OFFSET(guest_sysenter_cs, 920);
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CHECK_OFFSET(host_ia32_sysenter_cs, 924);
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CHECK_OFFSET(vmx_preemption_timer_value, 928);
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CHECK_OFFSET(virtual_processor_id, 960);
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CHECK_OFFSET(posted_intr_nv, 962);
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CHECK_OFFSET(guest_es_selector, 964);
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CHECK_OFFSET(guest_cs_selector, 966);
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CHECK_OFFSET(guest_ss_selector, 968);
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CHECK_OFFSET(guest_ds_selector, 970);
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CHECK_OFFSET(guest_fs_selector, 972);
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CHECK_OFFSET(guest_gs_selector, 974);
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CHECK_OFFSET(guest_ldtr_selector, 976);
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CHECK_OFFSET(guest_tr_selector, 978);
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CHECK_OFFSET(guest_intr_status, 980);
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CHECK_OFFSET(host_es_selector, 982);
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CHECK_OFFSET(host_cs_selector, 984);
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CHECK_OFFSET(host_ss_selector, 986);
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CHECK_OFFSET(host_ds_selector, 988);
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CHECK_OFFSET(host_fs_selector, 990);
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CHECK_OFFSET(host_gs_selector, 992);
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CHECK_OFFSET(host_tr_selector, 994);
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CHECK_OFFSET(guest_pml_index, 996);
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}
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extern const unsigned short vmcs_field_to_offset_table[];
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extern const unsigned int nr_vmcs12_fields;
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#define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
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static inline short vmcs_field_to_offset(unsigned long field)
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{
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unsigned short offset;
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unsigned int index;
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|
if (field >> 15)
|
|
return -ENOENT;
|
|
|
|
index = ROL16(field, 6);
|
|
if (index >= nr_vmcs12_fields)
|
|
return -ENOENT;
|
|
|
|
index = array_index_nospec(index, nr_vmcs12_fields);
|
|
offset = vmcs_field_to_offset_table[index];
|
|
if (offset == 0)
|
|
return -ENOENT;
|
|
return offset;
|
|
}
|
|
|
|
#undef ROL16
|
|
|
|
static inline u64 vmcs12_read_any(struct vmcs12 *vmcs12, unsigned long field,
|
|
u16 offset)
|
|
{
|
|
char *p = (char *)vmcs12 + offset;
|
|
|
|
switch (vmcs_field_width(field)) {
|
|
case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
|
|
return *((natural_width *)p);
|
|
case VMCS_FIELD_WIDTH_U16:
|
|
return *((u16 *)p);
|
|
case VMCS_FIELD_WIDTH_U32:
|
|
return *((u32 *)p);
|
|
case VMCS_FIELD_WIDTH_U64:
|
|
return *((u64 *)p);
|
|
default:
|
|
WARN_ON_ONCE(1);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
static inline void vmcs12_write_any(struct vmcs12 *vmcs12, unsigned long field,
|
|
u16 offset, u64 field_value)
|
|
{
|
|
char *p = (char *)vmcs12 + offset;
|
|
|
|
switch (vmcs_field_width(field)) {
|
|
case VMCS_FIELD_WIDTH_U16:
|
|
*(u16 *)p = field_value;
|
|
break;
|
|
case VMCS_FIELD_WIDTH_U32:
|
|
*(u32 *)p = field_value;
|
|
break;
|
|
case VMCS_FIELD_WIDTH_U64:
|
|
*(u64 *)p = field_value;
|
|
break;
|
|
case VMCS_FIELD_WIDTH_NATURAL_WIDTH:
|
|
*(natural_width *)p = field_value;
|
|
break;
|
|
default:
|
|
WARN_ON_ONCE(1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
#endif /* __KVM_X86_VMX_VMCS12_H */
|