mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 11:48:43 +07:00
f7df9be067
These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as well,
and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and
the Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition"
is added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7)
are supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported, which
in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet Processor",
following the IPQ806x that is used in many high-end WiFi routers. This one
integrates two ath10k wifi radios that were previously on separate chips.
Other boards that got added for existing chips are:
- On Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
- On Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
- On NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and
SoloX Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
- On Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
- On Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
- On Rockchips platform:
- mqmaker MiQi single-board computer
- On Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
- On Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC
single board computers
Across many platforms, bug fixes went in to address warnings that
dtc now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router),
Ti Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIVAwUAVzuXhGCrR//JCVInAQJXjhAA1bV0fbREflRQrlXdMb4rNesygH8ikaja
gOYHE1yO+tSitHZ5g4w2yAFIEK7DzFdO5rz53BEINZfLCj4LO4495/z9ipqZQEjC
rw5IL89jAn8x4wF791SHjLpmmNRbHN2vjLcsX3ShJIHckip/jIbiU2aFJuohA0TU
jxpPAZzhaKsu/rDaVzHMS/im4LbZQ2qI3DxUUn6Kt8c468i4Ns22sowqSjh2xO/X
YiwHD0eAvDrySfMGiNT82wMMTfMF2KfXZGB885isMP4hK8OIDrOnI5nM9rxyRFfu
N14o0+tN1S2JzBHnqOOpib6JxYyCVr+QTjsKGAyR5X1mGINIhX8f1gy0EvFFxXKT
rIATc5VTeo4gc1quij8RVtDEp/4iJ8GspH4WGMh1F8tjTe+WUxeSMkxdf6/QY1+Q
vZKT0KKihoJQu1xI62NjnaRbfbhwx2BSWehwgXVd72lD19dG5LPw+Nj6/8+Bgouc
YxJahgkB9MMtHoNp8huMg33Gr9a07/yVxc4CztXtf7N9phd0nEXov2iM1aBgazLU
8IVd3Z9lZA+4iGVcj3oBJ6K1IkiCmg2qoNyF6tcInR5vPjKLECuxyuZw8VKuUuHD
k/s/rymSGRlDN5i4F0h0r4MvQ9gkYfwk8xiL3ofmwYHwo103Q7b7Cw55XRk88EoB
appd5QA+pko=
=Nx46
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as
well, and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and the
Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition" is
added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7) are
supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported,
which in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet
Processor", following the IPQ806x that is used in many high-end WiFi
routers. This one integrates two ath10k wifi radios that were
previously on separate chips.
Other boards that got added for existing chips are:
Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and SoloX
Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
Rockchips platform:
- mqmaker MiQi single-board computer
Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC single board
computers
Across many platforms, bug fixes went in to address warnings that dtc
now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router), Ti
Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (458 commits)
ARM: dts: tango4: Import watchdog node
ARM: dts: tango4: Update cpus node for cpufreq
ARM: dts: tango4: Update DT to match clk driver
ARM: dts: tango4: Initial thermal support
arm/dst: Add Aspeed ast2500 device tree
arm/dts: Add Aspeed ast2400 device tree
ARM: sun7i: dt: Add pll3 and pll7 clocks
ARM: dts: sunxi: Add a olinuxino-lime2-emmc
ARM: dts: at91: sama5d4: add trng node
ARM: dts: at91: sama5d3: add trng node
ARM: dts: at91: sama5d2: add trng node
ARM: dts: at91: at91sam9g45 family: reduce the trng register map size
ARM: sun4i: dt: Add pll3 and pll7 clocks
ARM: sun5i: chip: Enable the TV Encoder
ARM: sun5i: r8: Add display blocks to the DTSI
ARM: sun5i: a13: Add display and TCON clocks
ARM: dts: ux500: configure the accelerometers open drain
ARM: mx5: dts: Enable USB OTG on M53EVK
ARM: dts: imx6ul-14x14-evk: Add audio support
ARM: dts: imx6qdl: Remove unneeded unit-addresses
...
1099 lines
26 KiB
Plaintext
1099 lines
26 KiB
Plaintext
/*
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* Device Tree Source for AM4372 SoC
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "ti,am4372", "ti,am43";
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interrupt-parent = <&wakeupgen>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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ethernet0 = &cpsw_emac0;
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ethernet1 = &cpsw_emac1;
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spi0 = &qspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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};
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48281000 0x1000>;
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interrupt-parent = <&gic>;
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};
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scu: scu@48240000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x48240000 0x100>;
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};
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global_timer: timer@48240200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x48240200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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local_timer: timer@48240600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x48240600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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l2-cache-controller@48242000 {
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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ocp {
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compatible = "ti,am4372-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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reg = <0x44000000 0x400000
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0x44800000 0x400000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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l4_wkup: l4_wkup@44c00000 {
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compatible = "ti,am4-l4-wkup", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x44c00000 0x287000>;
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wkup_m3: wkup_m3@100000 {
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compatible = "ti,am4372-wkup-m3";
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reg = <0x100000 0x4000>,
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<0x180000 0x2000>;
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reg-names = "umem", "dmem";
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ti,hwmods = "wkup_m3";
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ti,pm-firmware = "am335x-pm-firmware.elf";
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};
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prcm: prcm@1f0000 {
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compatible = "ti,am4-prcm";
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reg = <0x1f0000 0x11000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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prcm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prcm_clockdomains: clockdomains {
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};
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};
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scm: scm@210000 {
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compatible = "ti,am4-scm", "simple-bus";
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reg = <0x210000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x210000 0x4000>;
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am43xx_pinmux: pinmux@800 {
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compatible = "ti,am437-padconf",
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"pinctrl-single";
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reg = <0x800 0x31c>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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scm_conf: scm_conf@0 {
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compatible = "syscon";
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reg = <0x0 0x800>;
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#address-cells = <1>;
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#size-cells = <1>;
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scm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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wkup_m3_ipc: wkup_m3_ipc@1324 {
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compatible = "ti,am4372-wkup-m3-ipc";
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reg = <0x1324 0x44>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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ti,rproc = <&wkup_m3>;
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mboxes = <&mailbox &mbox_wkupm3>;
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};
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edma_xbar: dma-router@f90 {
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compatible = "ti,am335x-edma-crossbar";
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reg = <0xf90 0x40>;
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#dma-cells = <3>;
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dma-requests = <64>;
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dma-masters = <&edma>;
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};
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scm_clockdomains: clockdomains {
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};
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};
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};
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emif: emif@4c000000 {
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compatible = "ti,emif-am4372";
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reg = <0x4c000000 0x1000000>;
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ti,hwmods = "emif";
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};
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edma: edma@49000000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_ccint", "emda3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 0>;
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ti,edma-memcpy-channels = <58 59>;
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};
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edma_tptc0: tptc@49800000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x49800000 0x100000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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edma_tptc1: tptc@49900000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x49900000 0x100000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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edma_tptc2: tptc@49a00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc2";
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reg = <0x49a00000 0x100000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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uart0: serial@44e09000 {
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compatible = "ti,am4372-uart","ti,omap2-uart";
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reg = <0x44e09000 0x2000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart1";
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};
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uart1: serial@48022000 {
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compatible = "ti,am4372-uart","ti,omap2-uart";
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reg = <0x48022000 0x2000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart2";
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status = "disabled";
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};
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uart2: serial@48024000 {
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compatible = "ti,am4372-uart","ti,omap2-uart";
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reg = <0x48024000 0x2000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart3";
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status = "disabled";
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};
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uart3: serial@481a6000 {
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compatible = "ti,am4372-uart","ti,omap2-uart";
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reg = <0x481a6000 0x2000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart4";
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status = "disabled";
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};
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uart4: serial@481a8000 {
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compatible = "ti,am4372-uart","ti,omap2-uart";
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reg = <0x481a8000 0x2000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart5";
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status = "disabled";
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};
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uart5: serial@481aa000 {
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compatible = "ti,am4372-uart","ti,omap2-uart";
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reg = <0x481aa000 0x2000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart6";
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status = "disabled";
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};
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mailbox: mailbox@480C8000 {
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compatible = "ti,omap4-mailbox";
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reg = <0x480C8000 0x200>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "mailbox";
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#mbox-cells = <1>;
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <8>;
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mbox_wkupm3: wkup_m3 {
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ti,mbox-send-noirq;
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ti,mbox-tx = <0 0 0>;
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ti,mbox-rx = <0 0 3>;
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};
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};
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timer1: timer@44e31000 {
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compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
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reg = <0x44e31000 0x400>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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ti,timer-alwon;
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ti,hwmods = "timer1";
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};
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timer2: timer@48040000 {
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compatible = "ti,am4372-timer","ti,am335x-timer";
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reg = <0x48040000 0x400>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer2";
|
|
};
|
|
|
|
timer3: timer@48042000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x48042000 0x400>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer3";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer4: timer@48044000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x48044000 0x400>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,timer-pwm;
|
|
ti,hwmods = "timer4";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer5: timer@48046000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x48046000 0x400>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,timer-pwm;
|
|
ti,hwmods = "timer5";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer6: timer@48048000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x48048000 0x400>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,timer-pwm;
|
|
ti,hwmods = "timer6";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer7: timer@4804a000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x4804a000 0x400>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,timer-pwm;
|
|
ti,hwmods = "timer7";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer8: timer@481c1000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x481c1000 0x400>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer8";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer9: timer@4833d000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x4833d000 0x400>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer9";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer10: timer@4833f000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x4833f000 0x400>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer10";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer11: timer@48341000 {
|
|
compatible = "ti,am4372-timer","ti,am335x-timer";
|
|
reg = <0x48341000 0x400>;
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer11";
|
|
status = "disabled";
|
|
};
|
|
|
|
counter32k: counter@44e86000 {
|
|
compatible = "ti,am4372-counter32k","ti,omap-counter32k";
|
|
reg = <0x44e86000 0x40>;
|
|
ti,hwmods = "counter_32k";
|
|
};
|
|
|
|
rtc: rtc@44e3e000 {
|
|
compatible = "ti,am4372-rtc", "ti,am3352-rtc",
|
|
"ti,da830-rtc";
|
|
reg = <0x44e3e000 0x1000>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "rtc";
|
|
clocks = <&clk_32768_ck>;
|
|
clock-names = "int-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
wdt: wdt@44e35000 {
|
|
compatible = "ti,am4372-wdt","ti,omap3-wdt";
|
|
reg = <0x44e35000 0x1000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "wd_timer2";
|
|
};
|
|
|
|
gpio0: gpio@44e07000 {
|
|
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
|
reg = <0x44e07000 0x1000>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ti,hwmods = "gpio1";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio1: gpio@4804c000 {
|
|
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
|
reg = <0x4804c000 0x1000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ti,hwmods = "gpio2";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio2: gpio@481ac000 {
|
|
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
|
reg = <0x481ac000 0x1000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ti,hwmods = "gpio3";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio3: gpio@481ae000 {
|
|
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
|
reg = <0x481ae000 0x1000>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ti,hwmods = "gpio4";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio4: gpio@48320000 {
|
|
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
|
reg = <0x48320000 0x1000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ti,hwmods = "gpio5";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio5: gpio@48322000 {
|
|
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
|
reg = <0x48322000 0x1000>;
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
ti,hwmods = "gpio6";
|
|
status = "disabled";
|
|
};
|
|
|
|
hwspinlock: spinlock@480ca000 {
|
|
compatible = "ti,omap4-hwspinlock";
|
|
reg = <0x480ca000 0x1000>;
|
|
ti,hwmods = "spinlock";
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
i2c0: i2c@44e0b000 {
|
|
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
|
reg = <0x44e0b000 0x1000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "i2c1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@4802a000 {
|
|
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
|
reg = <0x4802a000 0x1000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "i2c2";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@4819c000 {
|
|
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
|
reg = <0x4819c000 0x1000>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "i2c3";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@48030000 {
|
|
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
|
reg = <0x48030000 0x400>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "spi0";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@48060000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x48060000 0x1000>;
|
|
ti,hwmods = "mmc1";
|
|
ti,dual-volt;
|
|
ti,needs-special-reset;
|
|
dmas = <&edma 24 0>,
|
|
<&edma 25 0>;
|
|
dma-names = "tx", "rx";
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc2: mmc@481d8000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x481d8000 0x1000>;
|
|
ti,hwmods = "mmc2";
|
|
ti,needs-special-reset;
|
|
dmas = <&edma 2 0>,
|
|
<&edma 3 0>;
|
|
dma-names = "tx", "rx";
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc3: mmc@47810000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x47810000 0x1000>;
|
|
ti,hwmods = "mmc3";
|
|
ti,needs-special-reset;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@481a0000 {
|
|
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
|
reg = <0x481a0000 0x400>;
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "spi1";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@481a2000 {
|
|
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
|
reg = <0x481a2000 0x400>;
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "spi2";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@481a4000 {
|
|
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
|
reg = <0x481a4000 0x400>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "spi3";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@48345000 {
|
|
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
|
reg = <0x48345000 0x400>;
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "spi4";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mac: ethernet@4a100000 {
|
|
compatible = "ti,am4372-cpsw","ti,cpsw";
|
|
reg = <0x4a100000 0x800
|
|
0x4a101200 0x100>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ti,hwmods = "cpgmac0";
|
|
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
|
|
<&dpll_clksel_mac_clk>;
|
|
clock-names = "fck", "cpts", "50mclk";
|
|
assigned-clocks = <&dpll_clksel_mac_clk>;
|
|
assigned-clock-rates = <50000000>;
|
|
status = "disabled";
|
|
cpdma_channels = <8>;
|
|
ale_entries = <1024>;
|
|
bd_ram_size = <0x2000>;
|
|
no_bd_ram = <0>;
|
|
rx_descs = <64>;
|
|
mac_control = <0x20>;
|
|
slaves = <2>;
|
|
active_slave = <0>;
|
|
cpts_clock_mult = <0x80000000>;
|
|
cpts_clock_shift = <29>;
|
|
ranges;
|
|
syscon = <&scm_conf>;
|
|
|
|
davinci_mdio: mdio@4a101000 {
|
|
compatible = "ti,am4372-mdio","ti,davinci_mdio";
|
|
reg = <0x4a101000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "davinci_mdio";
|
|
bus_freq = <1000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpsw_emac0: slave@4a100200 {
|
|
/* Filled in by U-Boot */
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
};
|
|
|
|
cpsw_emac1: slave@4a100300 {
|
|
/* Filled in by U-Boot */
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
};
|
|
|
|
phy_sel: cpsw-phy-sel@44e10650 {
|
|
compatible = "ti,am43xx-cpsw-phy-sel";
|
|
reg= <0x44e10650 0x4>;
|
|
reg-names = "gmii-sel";
|
|
};
|
|
};
|
|
|
|
epwmss0: epwmss@48300000 {
|
|
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
|
reg = <0x48300000 0x10>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "epwmss0";
|
|
status = "disabled";
|
|
|
|
ecap0: ecap@48300100 {
|
|
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48300100 0x80>;
|
|
ti,hwmods = "ecap0";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehrpwm0: pwm@48300200 {
|
|
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48300200 0x80>;
|
|
ti,hwmods = "ehrpwm0";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
epwmss1: epwmss@48302000 {
|
|
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
|
reg = <0x48302000 0x10>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "epwmss1";
|
|
status = "disabled";
|
|
|
|
ecap1: ecap@48302100 {
|
|
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48302100 0x80>;
|
|
ti,hwmods = "ecap1";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehrpwm1: pwm@48302200 {
|
|
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48302200 0x80>;
|
|
ti,hwmods = "ehrpwm1";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
epwmss2: epwmss@48304000 {
|
|
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
|
reg = <0x48304000 0x10>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "epwmss2";
|
|
status = "disabled";
|
|
|
|
ecap2: ecap@48304100 {
|
|
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48304100 0x80>;
|
|
ti,hwmods = "ecap2";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehrpwm2: pwm@48304200 {
|
|
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48304200 0x80>;
|
|
ti,hwmods = "ehrpwm2";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
epwmss3: epwmss@48306000 {
|
|
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
|
reg = <0x48306000 0x10>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "epwmss3";
|
|
status = "disabled";
|
|
|
|
ehrpwm3: pwm@48306200 {
|
|
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48306200 0x80>;
|
|
ti,hwmods = "ehrpwm3";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
epwmss4: epwmss@48308000 {
|
|
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
|
reg = <0x48308000 0x10>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "epwmss4";
|
|
status = "disabled";
|
|
|
|
ehrpwm4: pwm@48308200 {
|
|
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x48308200 0x80>;
|
|
ti,hwmods = "ehrpwm4";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
epwmss5: epwmss@4830a000 {
|
|
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
|
reg = <0x4830a000 0x10>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "epwmss5";
|
|
status = "disabled";
|
|
|
|
ehrpwm5: pwm@4830a200 {
|
|
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x4830a200 0x80>;
|
|
ti,hwmods = "ehrpwm5";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
tscadc: tscadc@44e0d000 {
|
|
compatible = "ti,am3359-tscadc";
|
|
reg = <0x44e0d000 0x1000>;
|
|
ti,hwmods = "adc_tsc";
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&adc_tsc_fck>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
|
|
tsc {
|
|
compatible = "ti,am3359-tsc";
|
|
};
|
|
|
|
adc {
|
|
#io-channel-cells = <1>;
|
|
compatible = "ti,am3359-adc";
|
|
};
|
|
|
|
};
|
|
|
|
sham: sham@53100000 {
|
|
compatible = "ti,omap5-sham";
|
|
ti,hwmods = "sham";
|
|
reg = <0x53100000 0x300>;
|
|
dmas = <&edma 36 0>;
|
|
dma-names = "rx";
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
aes: aes@53501000 {
|
|
compatible = "ti,omap4-aes";
|
|
ti,hwmods = "aes";
|
|
reg = <0x53501000 0xa0>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&edma 6 0>,
|
|
<&edma 5 0>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
des: des@53701000 {
|
|
compatible = "ti,omap4-des";
|
|
ti,hwmods = "des";
|
|
reg = <0x53701000 0xa0>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&edma 34 0>,
|
|
<&edma 33 0>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
mcasp0: mcasp@48038000 {
|
|
compatible = "ti,am33xx-mcasp-audio";
|
|
ti,hwmods = "mcasp0";
|
|
reg = <0x48038000 0x2000>,
|
|
<0x46000000 0x400000>;
|
|
reg-names = "mpu", "dat";
|
|
interrupts = <80>, <81>;
|
|
interrupt-names = "tx", "rx";
|
|
status = "disabled";
|
|
dmas = <&edma 8 2>,
|
|
<&edma 9 2>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
mcasp1: mcasp@4803C000 {
|
|
compatible = "ti,am33xx-mcasp-audio";
|
|
ti,hwmods = "mcasp1";
|
|
reg = <0x4803C000 0x2000>,
|
|
<0x46400000 0x400000>;
|
|
reg-names = "mpu", "dat";
|
|
interrupts = <82>, <83>;
|
|
interrupt-names = "tx", "rx";
|
|
status = "disabled";
|
|
dmas = <&edma 10 2>,
|
|
<&edma 11 2>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
elm: elm@48080000 {
|
|
compatible = "ti,am3352-elm";
|
|
reg = <0x48080000 0x2000>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "elm";
|
|
clocks = <&l4ls_gclk>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpmc: gpmc@50000000 {
|
|
compatible = "ti,am3352-gpmc";
|
|
ti,hwmods = "gpmc";
|
|
dmas = <&edma 52 0>;
|
|
dma-names = "rxtx";
|
|
clocks = <&l3s_gclk>;
|
|
clock-names = "fck";
|
|
reg = <0x50000000 0x2000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpmc,num-cs = <7>;
|
|
gpmc,num-waitpins = <2>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ocp2scp0: ocp2scp@483a8000 {
|
|
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "ocp2scp0";
|
|
|
|
usb2_phy1: phy@483a8000 {
|
|
compatible = "ti,am437x-usb2";
|
|
reg = <0x483a8000 0x8000>;
|
|
syscon-phy-power = <&scm_conf 0x620>;
|
|
clocks = <&usb_phy0_always_on_clk32k>,
|
|
<&usb_otg_ss0_refclk960m>;
|
|
clock-names = "wkupclk", "refclk";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ocp2scp1: ocp2scp@483e8000 {
|
|
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "ocp2scp1";
|
|
|
|
usb2_phy2: phy@483e8000 {
|
|
compatible = "ti,am437x-usb2";
|
|
reg = <0x483e8000 0x8000>;
|
|
syscon-phy-power = <&scm_conf 0x628>;
|
|
clocks = <&usb_phy1_always_on_clk32k>,
|
|
<&usb_otg_ss1_refclk960m>;
|
|
clock-names = "wkupclk", "refclk";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dwc3_1: omap_dwc3@48380000 {
|
|
compatible = "ti,am437x-dwc3";
|
|
ti,hwmods = "usb_otg_ss0";
|
|
reg = <0x48380000 0x10000>;
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
utmi-mode = <1>;
|
|
ranges;
|
|
|
|
usb1: usb@48390000 {
|
|
compatible = "synopsys,dwc3";
|
|
reg = <0x48390000 0x10000>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "peripheral",
|
|
"host",
|
|
"otg";
|
|
phys = <&usb2_phy1>;
|
|
phy-names = "usb2-phy";
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "otg";
|
|
status = "disabled";
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
};
|
|
};
|
|
|
|
dwc3_2: omap_dwc3@483c0000 {
|
|
compatible = "ti,am437x-dwc3";
|
|
ti,hwmods = "usb_otg_ss1";
|
|
reg = <0x483c0000 0x10000>;
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
utmi-mode = <1>;
|
|
ranges;
|
|
|
|
usb2: usb@483d0000 {
|
|
compatible = "synopsys,dwc3";
|
|
reg = <0x483d0000 0x10000>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "peripheral",
|
|
"host",
|
|
"otg";
|
|
phys = <&usb2_phy2>;
|
|
phy-names = "usb2-phy";
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "otg";
|
|
status = "disabled";
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
};
|
|
};
|
|
|
|
qspi: qspi@47900000 {
|
|
compatible = "ti,am4372-qspi";
|
|
reg = <0x47900000 0x100>,
|
|
<0x30000000 0x4000000>;
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "qspi";
|
|
interrupts = <0 138 0x4>;
|
|
num-cs = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hdq: hdq@48347000 {
|
|
compatible = "ti,am4372-hdq";
|
|
reg = <0x48347000 0x1000>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&func_12m_clk>;
|
|
clock-names = "fck";
|
|
ti,hwmods = "hdq1w";
|
|
status = "disabled";
|
|
};
|
|
|
|
dss: dss@4832a000 {
|
|
compatible = "ti,omap3-dss";
|
|
reg = <0x4832a000 0x200>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_core";
|
|
clocks = <&disp_clk>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
dispc: dispc@4832a400 {
|
|
compatible = "ti,omap3-dispc";
|
|
reg = <0x4832a400 0x400>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "dss_dispc";
|
|
clocks = <&disp_clk>;
|
|
clock-names = "fck";
|
|
};
|
|
|
|
rfbi: rfbi@4832a800 {
|
|
compatible = "ti,omap3-rfbi";
|
|
reg = <0x4832a800 0x100>;
|
|
ti,hwmods = "dss_rfbi";
|
|
clocks = <&disp_clk>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
ocmcram: ocmcram@40300000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x40300000 0x40000>; /* 256k */
|
|
};
|
|
|
|
dcan0: can@481cc000 {
|
|
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
|
|
ti,hwmods = "d_can0";
|
|
clocks = <&dcan0_fck>;
|
|
clock-names = "fck";
|
|
reg = <0x481cc000 0x2000>;
|
|
syscon-raminit = <&scm_conf 0x644 0>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dcan1: can@481d0000 {
|
|
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
|
|
ti,hwmods = "d_can1";
|
|
clocks = <&dcan1_fck>;
|
|
clock-names = "fck";
|
|
reg = <0x481d0000 0x2000>;
|
|
syscon-raminit = <&scm_conf 0x644 1>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vpfe0: vpfe@48326000 {
|
|
compatible = "ti,am437x-vpfe";
|
|
reg = <0x48326000 0x2000>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "vpfe0";
|
|
status = "disabled";
|
|
};
|
|
|
|
vpfe1: vpfe@48328000 {
|
|
compatible = "ti,am437x-vpfe";
|
|
reg = <0x48328000 0x2000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "vpfe1";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "am43xx-clocks.dtsi"
|