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c9c96ae2c5
This patch adds the clock and regulator consumer properties part of document for CPU DVFS clocks on Mediatek MT8173 SoC. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Acked-by: Michael Turquette <mturquette@baylibre.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
84 lines
2.3 KiB
Plaintext
84 lines
2.3 KiB
Plaintext
Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
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Required properties:
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
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- clock-names: Should contain the following:
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"cpu" - The multiplexer for clock input of CPU cluster.
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"intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
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source (usually MAINPLL) when the original CPU PLL is under
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transition and not stable yet.
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Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
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generic clock consumer properties.
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- proc-supply: Regulator for Vproc of CPU cluster.
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Optional properties:
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- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
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needs to do "voltage tracking" to step by step scale up/down Vproc and
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Vsram to fit SoC specific needs. When absent, the voltage scaling
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flow is handled by hardware, hence no software "voltage tracking" is
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needed.
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Example:
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--------
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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};
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&cpu0 {
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proc-supply = <&mt6397_vpca15_reg>;
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};
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&cpu1 {
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proc-supply = <&mt6397_vpca15_reg>;
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};
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&cpu2 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
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};
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&cpu3 {
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proc-supply = <&da9211_vcpu_reg>;
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sram-supply = <&mt6397_vsramca7_reg>;
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};
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