mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 21:15:44 +07:00
10cea23b6a
rts522a should use rts522a_pcr_ops, which is
diffrent with rts5227 in phy/hw init setting.
Fixes: ce6a5acc93 ("mfd: rtsx: Add support for rts522A")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20200326032618.20472-1-yuehaibing@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
408 lines
11 KiB
C
408 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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* Roger Tseng <rogerable@realtek.com>
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/rtsx_pci.h>
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#include "rtsx_pcr.h"
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static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
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{
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u8 val;
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rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
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return val & 0x0F;
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}
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static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
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{
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u8 driving_3v3[4][3] = {
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{0x13, 0x13, 0x13},
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{0x96, 0x96, 0x96},
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{0x7F, 0x7F, 0x7F},
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{0x96, 0x96, 0x96},
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};
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u8 driving_1v8[4][3] = {
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{0x99, 0x99, 0x99},
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{0xAA, 0xAA, 0xAA},
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{0xFE, 0xFE, 0xFE},
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{0xB3, 0xB3, 0xB3},
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};
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u8 (*driving)[3], drive_sel;
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if (voltage == OUTPUT_3V3) {
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driving = driving_3v3;
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drive_sel = pcr->sd30_drive_sel_3v3;
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} else {
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driving = driving_1v8;
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drive_sel = pcr->sd30_drive_sel_1v8;
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}
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
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0xFF, driving[drive_sel][0]);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
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0xFF, driving[drive_sel][1]);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
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0xFF, driving[drive_sel][2]);
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}
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static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
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{
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u32 reg;
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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if (!rtsx_vendor_setting_valid(reg))
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return;
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pcr->aspm_en = rtsx_reg_to_aspm(reg);
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pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
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pcr->card_drive_sel &= 0x3F;
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pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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}
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static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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/* Set relink_time to 0 */
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
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rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
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if (pm_state == HOST_ENTER_S3)
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rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x10);
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rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
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}
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static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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{
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u16 cap;
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rtsx_pci_init_cmd(pcr);
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/* Configure GPIO as output */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
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/* Reset ASPM state to default value */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
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/* Switch LDO3318 source from DV33 to card_3v3 */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
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/* LED shine disabled, set initial shine cycle period */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
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/* Configure LTR */
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pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
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if (cap & PCI_EXP_DEVCTL2_LTR_EN)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
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/* Configure OBFF */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
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/* Configure driving */
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rts5227_fill_driving(pcr, OUTPUT_3V3);
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/* Configure force_clock_req */
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
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{
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int err;
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err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
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if (err < 0)
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return err;
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/* Optimize RX sensitivity */
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return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
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}
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static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
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}
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static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
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}
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static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
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}
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static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
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}
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static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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int err;
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if (pcr->option.ocp_en)
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rtsx_pci_enable_ocp(pcr);
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_PARTIAL_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x02);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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/* To avoid too large in-rush current */
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msleep(20);
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x06);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
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SD_OUTPUT_EN, SD_OUTPUT_EN);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
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MS_OUTPUT_EN, MS_OUTPUT_EN);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
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{
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if (pcr->option.ocp_en)
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rtsx_pci_disable_ocp(pcr);
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rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
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PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
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rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
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return 0;
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}
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static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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int err;
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if (voltage == OUTPUT_3V3) {
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
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if (err < 0)
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return err;
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} else if (voltage == OUTPUT_1V8) {
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err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
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if (err < 0)
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return err;
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} else {
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return -EINVAL;
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}
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/* set pad drive */
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rtsx_pci_init_cmd(pcr);
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rts5227_fill_driving(pcr, voltage);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static const struct pcr_ops rts5227_pcr_ops = {
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.fetch_vendor_settings = rts5227_fetch_vendor_settings,
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.extra_init_hw = rts5227_extra_init_hw,
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.optimize_phy = rts5227_optimize_phy,
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.turn_on_led = rts5227_turn_on_led,
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.turn_off_led = rts5227_turn_off_led,
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.enable_auto_blink = rts5227_enable_auto_blink,
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.disable_auto_blink = rts5227_disable_auto_blink,
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.card_power_on = rts5227_card_power_on,
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.card_power_off = rts5227_card_power_off,
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.switch_output_voltage = rts5227_switch_output_voltage,
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.cd_deglitch = NULL,
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.conv_clk_and_div_n = NULL,
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.force_power_down = rts5227_force_power_down,
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};
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/* SD Pull Control Enable:
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* SD_DAT[3:0] ==> pull up
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* SD_CD ==> pull up
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* SD_WP ==> pull up
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* SD_CMD ==> pull up
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* SD_CLK ==> pull down
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*/
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static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
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0,
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};
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/* SD Pull Control Disable:
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* SD_DAT[3:0] ==> pull down
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* SD_CD ==> pull up
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* SD_WP ==> pull down
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* SD_CMD ==> pull down
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* SD_CLK ==> pull down
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*/
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static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
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0,
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};
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/* MS Pull Control Enable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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/* MS Pull Control Disable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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void rts5227_init_params(struct rtsx_pcr *pcr)
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{
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pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
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pcr->num_slots = 2;
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pcr->ops = &rts5227_pcr_ops;
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pcr->flags = 0;
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pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
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pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
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pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
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pcr->aspm_en = ASPM_L1_EN;
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pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
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pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
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pcr->ic_version = rts5227_get_ic_version(pcr);
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pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
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pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
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pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
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pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
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pcr->reg_pm_ctrl3 = PM_CTRL3;
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}
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static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
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{
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int err;
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err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
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0x00);
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if (err < 0)
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return err;
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if (is_version(pcr, 0x522A, IC_VER_A)) {
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err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
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PHY_RCR2_INIT_27S);
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if (err)
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return err;
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rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
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rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
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rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
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rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
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}
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return 0;
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}
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static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rts5227_extra_init_hw(pcr);
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rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
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FUNC_FORCE_UPME_XMT_DBG);
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rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
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rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
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rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
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return 0;
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}
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static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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int err;
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if (voltage == OUTPUT_3V3) {
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
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if (err < 0)
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return err;
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} else if (voltage == OUTPUT_1V8) {
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err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
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if (err < 0)
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return err;
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} else {
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return -EINVAL;
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}
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/* set pad drive */
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rtsx_pci_init_cmd(pcr);
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rts5227_fill_driving(pcr, voltage);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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/* rts522a operations mainly derived from rts5227, except phy/hw init setting.
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*/
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static const struct pcr_ops rts522a_pcr_ops = {
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.fetch_vendor_settings = rts5227_fetch_vendor_settings,
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.extra_init_hw = rts522a_extra_init_hw,
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.optimize_phy = rts522a_optimize_phy,
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.turn_on_led = rts5227_turn_on_led,
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.turn_off_led = rts5227_turn_off_led,
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.enable_auto_blink = rts5227_enable_auto_blink,
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.disable_auto_blink = rts5227_disable_auto_blink,
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.card_power_on = rts5227_card_power_on,
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.card_power_off = rts5227_card_power_off,
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.switch_output_voltage = rts522a_switch_output_voltage,
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.cd_deglitch = NULL,
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.conv_clk_and_div_n = NULL,
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.force_power_down = rts5227_force_power_down,
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};
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void rts522a_init_params(struct rtsx_pcr *pcr)
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{
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rts5227_init_params(pcr);
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pcr->ops = &rts522a_pcr_ops;
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pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
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pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
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pcr->option.ocp_en = 1;
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if (pcr->option.ocp_en)
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pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
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pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
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pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
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}
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