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f7cd2d835e
SPC(Serial Power Controller) on TC2 also controls the CPU performance operating points which is essential to provide CPU DVFS. The M3 microcontroller provides two sets of eight performance values, one set for each cluster (CA15 or CA7). Each of this value contains the frequency(kHz) and voltage(mV) at that performance level. It expects these performance level to be passed through the SPC PERF_LVL registers. This patch adds support to populate these performance levels from M3, build the mapping to CPU OPPs at the boot and then use it to get and set the CPU performance level runtime. Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Pawel Moll <Pawel.Moll@arm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
25 lines
805 B
C
25 lines
805 B
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2012 ARM Limited
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*/
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#ifndef __SPC_H_
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#define __SPC_H_
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int __init ve_spc_init(void __iomem *base, u32 a15_clusid, int irq);
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void ve_spc_global_wakeup_irq(bool set);
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void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set);
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void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr);
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void ve_spc_powerdown(u32 cluster, bool enable);
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#endif
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