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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cb1d9f6dda
Rockchip socs often have some tiny number of muxes not controlled from the core clock controller but through bits set in the general register files. Add a clock-type that can control these as well, so that we don't need to work around them being absent. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/*
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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struct rockchip_muxgrf_clock {
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struct clk_hw hw;
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struct regmap *regmap;
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u32 reg;
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u32 shift;
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u32 width;
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int flags;
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};
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#define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw)
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static u8 rockchip_muxgrf_get_parent(struct clk_hw *hw)
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{
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struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
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unsigned int mask = GENMASK(mux->width - 1, 0);
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unsigned int val;
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regmap_read(mux->regmap, mux->reg, &val);
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val >>= mux->shift;
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val &= mask;
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return val;
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}
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static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index)
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{
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struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
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unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
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unsigned int val;
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val = index;
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val <<= mux->shift;
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if (mux->flags & CLK_MUX_HIWORD_MASK)
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return regmap_write(mux->regmap, mux->reg, val | (mask << 16));
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else
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return regmap_update_bits(mux->regmap, mux->reg, mask, val);
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}
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static const struct clk_ops rockchip_muxgrf_clk_ops = {
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.get_parent = rockchip_muxgrf_get_parent,
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.set_parent = rockchip_muxgrf_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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struct clk *rockchip_clk_register_muxgrf(const char *name,
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const char *const *parent_names, u8 num_parents,
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int flags, struct regmap *regmap, int reg,
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int shift, int width, int mux_flags)
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{
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struct rockchip_muxgrf_clock *muxgrf_clock;
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struct clk_init_data init;
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struct clk *clk;
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if (IS_ERR(regmap)) {
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pr_err("%s: regmap not available\n", __func__);
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return ERR_PTR(-ENOTSUPP);
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}
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muxgrf_clock = kmalloc(sizeof(*muxgrf_clock), GFP_KERNEL);
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if (!muxgrf_clock)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags;
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init.num_parents = num_parents;
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init.parent_names = parent_names;
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init.ops = &rockchip_muxgrf_clk_ops;
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muxgrf_clock->hw.init = &init;
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muxgrf_clock->regmap = regmap;
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muxgrf_clock->reg = reg;
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muxgrf_clock->shift = shift;
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muxgrf_clock->width = width;
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muxgrf_clock->flags = mux_flags;
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clk = clk_register(NULL, &muxgrf_clock->hw);
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if (IS_ERR(clk))
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kfree(muxgrf_clock);
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return clk;
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}
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