Eugeniy Paltsev f6a09bace0 ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk ... Add core pll node (core_clk) to manage cpu frequency. core_clk represents pll itself. input_clk represents clock signal source (basically xtal) which comes to pll input. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2017-09-01 11:26:25 -07:00
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dts	ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk	2017-09-01 11:26:25 -07:00
.gitignore	ARC: add uImage to .gitignore	2014-03-26 14:31:26 +05:30
Makefile	ARC: [build] Support gz, lzma compressed uImage	2016-10-16 15:49:07 -07:00