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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ca2a88f56a
- Various cleanups especially in NAND tests
- Add support for NAND flash on BCMA bus
- DT support for sh_flctl and denali NAND drivers
- Kill obsolete/superceded drivers (fortunet, nomadik_nand)
- Fix JFFS2 locking bug in ENOMEM failure path
- New SPI flash chips, as usual
- Support writing in 'reliable mode' for DiskOnChip G4
- Debugfs support in nandsim
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iEYEABECAAYFAlDSAa4ACgkQdwG7hYl686MMcACeNYa//ghPtccb5L+IRXsqaFDL
Yi4AoLWOaOjN8qM4KUF/bfMEkwNGAePz
=DaAQ
-----END PGP SIGNATURE-----
Merge tag 'for-linus-20121219' of git://git.infradead.org/linux-mtd
Pull MTD updates from David Woodhouse:
- Various cleanups especially in NAND tests
- Add support for NAND flash on BCMA bus
- DT support for sh_flctl and denali NAND drivers
- Kill obsolete/superceded drivers (fortunet, nomadik_nand)
- Fix JFFS2 locking bug in ENOMEM failure path
- New SPI flash chips, as usual
- Support writing in 'reliable mode' for DiskOnChip G4
- Debugfs support in nandsim
* tag 'for-linus-20121219' of git://git.infradead.org/linux-mtd: (96 commits)
mtd: nand: typo in nand_id_has_period() comments
mtd: nand/gpio: use io{read,write}*_rep accessors
mtd: block2mtd: throttle writes by calling balance_dirty_pages_ratelimited.
mtd: nand: gpmi: reset BCH earlier, too, to avoid NAND startup problems
mtd: nand/docg4: fix and improve read of factory bbt
mtd: nand/docg4: reserve bb marker area in ecclayout
mtd: nand/docg4: add support for writing in reliable mode
mtd: mxc_nand: reorder part_probes to let cmdline override other sources
mtd: mxc_nand: fix unbalanced clk_disable() in error path
mtd: nandsim: Introduce debugfs infrastructure
mtd: physmap_of: error checking to prevent a NULL pointer dereference
mtg: docg3: potential divide by zero in doc_write_oob()
mtd: bcm47xxnflash: writing support
mtd: tests/read: initialize buffer for whole next page
mtd: at91: atmel_nand: return bit flips for the PMECC read_page()
mtd: fix recovery after failed write-buffer operation in cfi_cmdset_0002.c
mtd: nand: onfi need to be probed in 8 bits mode
mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width
mtd: nand: print flash size during detection
mted: nand_wait_ready timeout fix
...
148 lines
3.5 KiB
Plaintext
148 lines
3.5 KiB
Plaintext
/*
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* DTS file for SPEAr320 SoC
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*
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* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "spear3xx.dtsi"
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/ {
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x40000000 0x40000000 0x80000000
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0xd0000000 0xd0000000 0x30000000>;
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pinmux: pinmux@b3000000 {
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compatible = "st,spear320-pinmux";
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reg = <0xb3000000 0x1000>;
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#gpio-range-cells = <2>;
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};
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clcd@90000000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0x90000000 0x1000>;
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interrupts = <8>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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fsmc: flash@4c000000 {
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compatible = "st,spear600-fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x4c000000 0x1000 /* FSMC Register */
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0x50000000 0x0010 /* NAND Base DATA */
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0x50020000 0x0010 /* NAND Base ADDR */
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0x50010000 0x0010>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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status = "disabled";
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};
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sdhci@70000000 {
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compatible = "st,sdhci-spear";
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reg = <0x70000000 0x100>;
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interrupts = <10>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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shirq: interrupt-controller@0xb3000000 {
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compatible = "st,spear320-shirq";
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reg = <0xb3000000 0x1000>;
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interrupts = <30 28 29 1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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spi1: spi@a5000000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xa5000000 0x1000>;
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interrupts = <15>;
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interrupt-parent = <&shirq>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@a6000000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xa6000000 0x1000>;
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interrupts = <16>;
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interrupt-parent = <&shirq>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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pwm: pwm@a8000000 {
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compatible ="st,spear-pwm";
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reg = <0xa8000000 0x1000>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0xa0000000 0xa0000000 0x20000000
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0xd0000000 0xd0000000 0x30000000>;
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i2c1: i2c@a7000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xa7000000 0x1000>;
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interrupts = <21>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@a3000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xa3000000 0x1000>;
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interrupts = <13>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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serial@a4000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xa4000000 0x1000>;
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interrupts = <14>;
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interrupt-parent = <&shirq>;
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status = "disabled";
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};
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gpiopinctrl: gpio@b3000000 {
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compatible = "st,spear-plgpio";
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reg = <0xb3000000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinmux 0 102>;
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status = "disabled";
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st-plgpio,ngpio = <102>;
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st-plgpio,enb-reg = <0x24>;
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st-plgpio,wdata-reg = <0x34>;
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st-plgpio,dir-reg = <0x44>;
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st-plgpio,ie-reg = <0x64>;
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st-plgpio,rdata-reg = <0x54>;
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st-plgpio,mis-reg = <0x84>;
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st-plgpio,eit-reg = <0x94>;
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};
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};
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};
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};
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