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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 09:42:17 +07:00
832ad0e3da
The Keystone QMSS driver is pretty damaged, in the sense that it does things like this: irq_set_affinity_hint(irq, to_cpumask(&cpu_map)); where cpu_map is a local variable. As we leave the function, this will point to nowhere-land, and things will end-up badly. Instead, let's use a proper cpumask that gets allocated, giving the driver a chance to actually work with things like irqbalance as well as have a hypothetical 64bit future. Cc: stable@vger.kernel.org Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
396 lines
9.7 KiB
C
396 lines
9.7 KiB
C
/*
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* Keystone Navigator QMSS driver internal header
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*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
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* Author: Sandeep Nair <sandeep_n@ti.com>
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* Cyril Chemparathy <cyril@ti.com>
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __KNAV_QMSS_H__
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#define __KNAV_QMSS_H__
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#include <linux/percpu.h>
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#define THRESH_GTE BIT(7)
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#define THRESH_LT 0
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#define PDSP_CTRL_PC_MASK 0xffff0000
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#define PDSP_CTRL_SOFT_RESET BIT(0)
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#define PDSP_CTRL_ENABLE BIT(1)
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#define PDSP_CTRL_RUNNING BIT(15)
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#define ACC_MAX_CHANNEL 48
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#define ACC_DEFAULT_PERIOD 25 /* usecs */
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#define ACC_CHANNEL_INT_BASE 2
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#define ACC_LIST_ENTRY_TYPE 1
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#define ACC_LIST_ENTRY_WORDS (1 << ACC_LIST_ENTRY_TYPE)
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#define ACC_LIST_ENTRY_QUEUE_IDX 0
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#define ACC_LIST_ENTRY_DESC_IDX (ACC_LIST_ENTRY_WORDS - 1)
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#define ACC_CMD_DISABLE_CHANNEL 0x80
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#define ACC_CMD_ENABLE_CHANNEL 0x81
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#define ACC_CFG_MULTI_QUEUE BIT(21)
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#define ACC_INTD_OFFSET_EOI (0x0010)
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#define ACC_INTD_OFFSET_COUNT(ch) (0x0300 + 4 * (ch))
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#define ACC_INTD_OFFSET_STATUS(ch) (0x0200 + 4 * ((ch) / 32))
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#define RANGE_MAX_IRQS 64
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#define ACC_DESCS_MAX SZ_1K
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#define ACC_DESCS_MASK (ACC_DESCS_MAX - 1)
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#define DESC_SIZE_MASK 0xful
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#define DESC_PTR_MASK (~DESC_SIZE_MASK)
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#define KNAV_NAME_SIZE 32
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enum knav_acc_result {
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ACC_RET_IDLE,
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ACC_RET_SUCCESS,
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ACC_RET_INVALID_COMMAND,
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ACC_RET_INVALID_CHANNEL,
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ACC_RET_INACTIVE_CHANNEL,
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ACC_RET_ACTIVE_CHANNEL,
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ACC_RET_INVALID_QUEUE,
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ACC_RET_INVALID_RET,
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};
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struct knav_reg_config {
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u32 revision;
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u32 __pad1;
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u32 divert;
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u32 link_ram_base0;
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u32 link_ram_size0;
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u32 link_ram_base1;
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u32 __pad2[2];
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u32 starvation[0];
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};
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struct knav_reg_region {
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u32 base;
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u32 start_index;
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u32 size_count;
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u32 __pad;
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};
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struct knav_reg_pdsp_regs {
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u32 control;
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u32 status;
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u32 cycle_count;
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u32 stall_count;
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};
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struct knav_reg_acc_command {
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u32 command;
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u32 queue_mask;
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u32 list_dma;
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u32 queue_num;
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u32 timer_config;
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};
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struct knav_link_ram_block {
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dma_addr_t dma;
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void *virt;
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size_t size;
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};
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struct knav_acc_info {
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u32 pdsp_id;
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u32 start_channel;
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u32 list_entries;
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u32 pacing_mode;
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u32 timer_count;
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int mem_size;
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int list_size;
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struct knav_pdsp_info *pdsp;
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};
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struct knav_acc_channel {
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u32 channel;
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u32 list_index;
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u32 open_mask;
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u32 *list_cpu[2];
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dma_addr_t list_dma[2];
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char name[KNAV_NAME_SIZE];
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atomic_t retrigger_count;
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};
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struct knav_pdsp_info {
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const char *name;
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struct knav_reg_pdsp_regs __iomem *regs;
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union {
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void __iomem *command;
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struct knav_reg_acc_command __iomem *acc_command;
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u32 __iomem *qos_command;
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};
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void __iomem *intd;
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u32 __iomem *iram;
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u32 id;
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struct list_head list;
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bool loaded;
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bool started;
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};
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struct knav_qmgr_info {
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unsigned start_queue;
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unsigned num_queues;
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struct knav_reg_config __iomem *reg_config;
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struct knav_reg_region __iomem *reg_region;
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struct knav_reg_queue __iomem *reg_push, *reg_pop, *reg_peek;
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void __iomem *reg_status;
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struct list_head list;
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};
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#define KNAV_NUM_LINKRAM 2
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/**
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* struct knav_queue_stats: queue statistics
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* pushes: number of push operations
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* pops: number of pop operations
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* push_errors: number of push errors
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* pop_errors: number of pop errors
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* notifies: notifier counts
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*/
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struct knav_queue_stats {
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unsigned int pushes;
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unsigned int pops;
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unsigned int push_errors;
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unsigned int pop_errors;
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unsigned int notifies;
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};
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/**
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* struct knav_reg_queue: queue registers
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* @entry_count: valid entries in the queue
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* @byte_count: total byte count in thhe queue
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* @packet_size: packet size for the queue
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* @ptr_size_thresh: packet pointer size threshold
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*/
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struct knav_reg_queue {
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u32 entry_count;
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u32 byte_count;
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u32 packet_size;
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u32 ptr_size_thresh;
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};
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/**
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* struct knav_region: qmss region info
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* @dma_start, dma_end: start and end dma address
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* @virt_start, virt_end: start and end virtual address
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* @desc_size: descriptor size
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* @used_desc: consumed descriptors
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* @id: region number
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* @num_desc: total descriptors
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* @link_index: index of the first descriptor
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* @name: region name
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* @list: instance in the device's region list
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* @pools: list of descriptor pools in the region
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*/
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struct knav_region {
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dma_addr_t dma_start, dma_end;
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void *virt_start, *virt_end;
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unsigned desc_size;
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unsigned used_desc;
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unsigned id;
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unsigned num_desc;
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unsigned link_index;
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const char *name;
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struct list_head list;
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struct list_head pools;
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};
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/**
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* struct knav_pool: qmss pools
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* @dev: device pointer
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* @region: qmss region info
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* @queue: queue registers
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* @kdev: qmss device pointer
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* @region_offset: offset from the base
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* @num_desc: total descriptors
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* @desc_size: descriptor size
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* @region_id: region number
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* @name: pool name
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* @list: list head
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* @region_inst: instance in the region's pool list
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*/
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struct knav_pool {
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struct device *dev;
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struct knav_region *region;
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struct knav_queue *queue;
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struct knav_device *kdev;
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int region_offset;
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int num_desc;
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int desc_size;
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int region_id;
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const char *name;
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struct list_head list;
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struct list_head region_inst;
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};
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/**
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* struct knav_queue_inst: qmss queue instance properties
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* @descs: descriptor pointer
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* @desc_head, desc_tail, desc_count: descriptor counters
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* @acc: accumulator channel pointer
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* @kdev: qmss device pointer
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* @range: range info
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* @qmgr: queue manager info
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* @id: queue instance id
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* @irq_num: irq line number
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* @notify_needed: notifier needed based on queue type
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* @num_notifiers: total notifiers
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* @handles: list head
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* @name: queue instance name
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* @irq_name: irq line name
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*/
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struct knav_queue_inst {
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u32 *descs;
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atomic_t desc_head, desc_tail, desc_count;
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struct knav_acc_channel *acc;
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struct knav_device *kdev;
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struct knav_range_info *range;
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struct knav_qmgr_info *qmgr;
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u32 id;
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int irq_num;
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int notify_needed;
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atomic_t num_notifiers;
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struct list_head handles;
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const char *name;
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const char *irq_name;
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};
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/**
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* struct knav_queue: qmss queue properties
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* @reg_push, reg_pop, reg_peek: push, pop queue registers
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* @inst: qmss queue instance properties
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* @notifier_fn: notifier function
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* @notifier_fn_arg: notifier function argument
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* @notifier_enabled: notier enabled for a give queue
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* @rcu: rcu head
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* @flags: queue flags
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* @list: list head
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*/
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struct knav_queue {
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struct knav_reg_queue __iomem *reg_push, *reg_pop, *reg_peek;
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struct knav_queue_inst *inst;
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struct knav_queue_stats __percpu *stats;
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knav_queue_notify_fn notifier_fn;
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void *notifier_fn_arg;
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atomic_t notifier_enabled;
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struct rcu_head rcu;
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unsigned flags;
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struct list_head list;
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};
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enum qmss_version {
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QMSS,
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QMSS_66AK2G,
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};
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struct knav_device {
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struct device *dev;
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unsigned base_id;
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unsigned num_queues;
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unsigned num_queues_in_use;
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unsigned inst_shift;
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struct knav_link_ram_block link_rams[KNAV_NUM_LINKRAM];
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void *instances;
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struct list_head regions;
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struct list_head queue_ranges;
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struct list_head pools;
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struct list_head pdsps;
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struct list_head qmgrs;
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enum qmss_version version;
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};
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struct knav_range_ops {
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int (*init_range)(struct knav_range_info *range);
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int (*free_range)(struct knav_range_info *range);
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int (*init_queue)(struct knav_range_info *range,
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struct knav_queue_inst *inst);
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int (*open_queue)(struct knav_range_info *range,
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struct knav_queue_inst *inst, unsigned flags);
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int (*close_queue)(struct knav_range_info *range,
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struct knav_queue_inst *inst);
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int (*set_notify)(struct knav_range_info *range,
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struct knav_queue_inst *inst, bool enabled);
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};
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struct knav_irq_info {
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int irq;
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struct cpumask *cpu_mask;
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};
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struct knav_range_info {
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const char *name;
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struct knav_device *kdev;
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unsigned queue_base;
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unsigned num_queues;
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void *queue_base_inst;
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unsigned flags;
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struct list_head list;
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struct knav_range_ops *ops;
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struct knav_acc_info acc_info;
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struct knav_acc_channel *acc;
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unsigned num_irqs;
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struct knav_irq_info irqs[RANGE_MAX_IRQS];
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};
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#define RANGE_RESERVED BIT(0)
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#define RANGE_HAS_IRQ BIT(1)
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#define RANGE_HAS_ACCUMULATOR BIT(2)
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#define RANGE_MULTI_QUEUE BIT(3)
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#define for_each_region(kdev, region) \
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list_for_each_entry(region, &kdev->regions, list)
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#define first_region(kdev) \
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list_first_entry_or_null(&kdev->regions, \
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struct knav_region, list)
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#define for_each_queue_range(kdev, range) \
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list_for_each_entry(range, &kdev->queue_ranges, list)
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#define first_queue_range(kdev) \
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list_first_entry_or_null(&kdev->queue_ranges, \
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struct knav_range_info, list)
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#define for_each_pool(kdev, pool) \
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list_for_each_entry(pool, &kdev->pools, list)
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#define for_each_pdsp(kdev, pdsp) \
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list_for_each_entry(pdsp, &kdev->pdsps, list)
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#define for_each_qmgr(kdev, qmgr) \
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list_for_each_entry(qmgr, &kdev->qmgrs, list)
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static inline struct knav_pdsp_info *
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knav_find_pdsp(struct knav_device *kdev, unsigned pdsp_id)
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{
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struct knav_pdsp_info *pdsp;
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for_each_pdsp(kdev, pdsp)
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if (pdsp_id == pdsp->id)
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return pdsp;
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return NULL;
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}
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extern int knav_init_acc_range(struct knav_device *kdev,
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struct device_node *node,
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struct knav_range_info *range);
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extern void knav_queue_notify(struct knav_queue_inst *inst);
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#endif /* __KNAV_QMSS_H__ */
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