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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 01:46:45 +07:00
842dfc11ea
Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:
{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
LD arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
arch/mips/alchemy/common/sleeper.o uses -mhard-float
To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS; but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
133 lines
3.7 KiB
ArmAsm
133 lines
3.7 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1998 by Ralf Baechle
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*
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* Multi-arch abstraction and asm macros for easier reading:
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*
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* Further modifications to make this work:
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* Copyright (c) 1998 Harald Koerfgen
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*/
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#include <asm/asm.h>
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#include <asm/errno.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#define EX(a,b) \
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9: a,##b; \
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.section __ex_table,"a"; \
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PTR 9b,bad_stack; \
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.previous
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.set noreorder
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.set mips1
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/* Save floating point context */
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LEAF(_save_fp_context)
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.set push
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SET_HARDFLOAT
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li v0, 0 # assume success
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cfc1 t1,fcr31
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EX(swc1 $f0,(SC_FPREGS+0)(a0))
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EX(swc1 $f1,(SC_FPREGS+8)(a0))
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EX(swc1 $f2,(SC_FPREGS+16)(a0))
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EX(swc1 $f3,(SC_FPREGS+24)(a0))
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EX(swc1 $f4,(SC_FPREGS+32)(a0))
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EX(swc1 $f5,(SC_FPREGS+40)(a0))
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EX(swc1 $f6,(SC_FPREGS+48)(a0))
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EX(swc1 $f7,(SC_FPREGS+56)(a0))
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EX(swc1 $f8,(SC_FPREGS+64)(a0))
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EX(swc1 $f9,(SC_FPREGS+72)(a0))
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EX(swc1 $f10,(SC_FPREGS+80)(a0))
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EX(swc1 $f11,(SC_FPREGS+88)(a0))
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EX(swc1 $f12,(SC_FPREGS+96)(a0))
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EX(swc1 $f13,(SC_FPREGS+104)(a0))
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EX(swc1 $f14,(SC_FPREGS+112)(a0))
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EX(swc1 $f15,(SC_FPREGS+120)(a0))
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EX(swc1 $f16,(SC_FPREGS+128)(a0))
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EX(swc1 $f17,(SC_FPREGS+136)(a0))
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EX(swc1 $f18,(SC_FPREGS+144)(a0))
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EX(swc1 $f19,(SC_FPREGS+152)(a0))
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EX(swc1 $f20,(SC_FPREGS+160)(a0))
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EX(swc1 $f21,(SC_FPREGS+168)(a0))
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EX(swc1 $f22,(SC_FPREGS+176)(a0))
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EX(swc1 $f23,(SC_FPREGS+184)(a0))
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EX(swc1 $f24,(SC_FPREGS+192)(a0))
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EX(swc1 $f25,(SC_FPREGS+200)(a0))
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EX(swc1 $f26,(SC_FPREGS+208)(a0))
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EX(swc1 $f27,(SC_FPREGS+216)(a0))
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EX(swc1 $f28,(SC_FPREGS+224)(a0))
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EX(swc1 $f29,(SC_FPREGS+232)(a0))
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EX(swc1 $f30,(SC_FPREGS+240)(a0))
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EX(swc1 $f31,(SC_FPREGS+248)(a0))
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EX(sw t1,(SC_FPC_CSR)(a0))
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cfc1 t0,$0 # implementation/version
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jr ra
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.set pop
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.set nomacro
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EX(sw t0,(SC_FPC_EIR)(a0))
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.set macro
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END(_save_fp_context)
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/*
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* Restore FPU state:
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* - fp gp registers
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* - cp1 status/control register
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*
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* We base the decision which registers to restore from the signal stack
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* frame on the current content of c0_status, not on the content of the
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* stack frame which might have been changed by the user.
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*/
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LEAF(_restore_fp_context)
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.set push
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SET_HARDFLOAT
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li v0, 0 # assume success
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EX(lw t0,(SC_FPC_CSR)(a0))
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EX(lwc1 $f0,(SC_FPREGS+0)(a0))
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EX(lwc1 $f1,(SC_FPREGS+8)(a0))
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EX(lwc1 $f2,(SC_FPREGS+16)(a0))
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EX(lwc1 $f3,(SC_FPREGS+24)(a0))
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EX(lwc1 $f4,(SC_FPREGS+32)(a0))
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EX(lwc1 $f5,(SC_FPREGS+40)(a0))
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EX(lwc1 $f6,(SC_FPREGS+48)(a0))
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EX(lwc1 $f7,(SC_FPREGS+56)(a0))
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EX(lwc1 $f8,(SC_FPREGS+64)(a0))
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EX(lwc1 $f9,(SC_FPREGS+72)(a0))
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EX(lwc1 $f10,(SC_FPREGS+80)(a0))
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EX(lwc1 $f11,(SC_FPREGS+88)(a0))
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EX(lwc1 $f12,(SC_FPREGS+96)(a0))
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EX(lwc1 $f13,(SC_FPREGS+104)(a0))
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EX(lwc1 $f14,(SC_FPREGS+112)(a0))
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EX(lwc1 $f15,(SC_FPREGS+120)(a0))
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EX(lwc1 $f16,(SC_FPREGS+128)(a0))
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EX(lwc1 $f17,(SC_FPREGS+136)(a0))
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EX(lwc1 $f18,(SC_FPREGS+144)(a0))
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EX(lwc1 $f19,(SC_FPREGS+152)(a0))
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EX(lwc1 $f20,(SC_FPREGS+160)(a0))
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EX(lwc1 $f21,(SC_FPREGS+168)(a0))
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EX(lwc1 $f22,(SC_FPREGS+176)(a0))
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EX(lwc1 $f23,(SC_FPREGS+184)(a0))
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EX(lwc1 $f24,(SC_FPREGS+192)(a0))
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EX(lwc1 $f25,(SC_FPREGS+200)(a0))
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EX(lwc1 $f26,(SC_FPREGS+208)(a0))
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EX(lwc1 $f27,(SC_FPREGS+216)(a0))
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EX(lwc1 $f28,(SC_FPREGS+224)(a0))
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EX(lwc1 $f29,(SC_FPREGS+232)(a0))
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EX(lwc1 $f30,(SC_FPREGS+240)(a0))
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EX(lwc1 $f31,(SC_FPREGS+248)(a0))
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jr ra
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ctc1 t0,fcr31
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.set pop
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END(_restore_fp_context)
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.set reorder
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.type fault@function
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.ent fault
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fault: li v0, -EFAULT
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jr ra
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.end fault
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