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f6470c9bcc
Split igt_atomic_reset selftests into separate full & engines parts, so we can move former to the dedicated reset selftests file. While here change engines test to loop first over atomic phases and then loop over available engines. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190522193203.23932-3-michal.wajdeczko@intel.com
117 lines
2.5 KiB
C
117 lines
2.5 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2018 Intel Corporation
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*/
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#include "i915_selftest.h"
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#include "selftests/igt_reset.h"
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#include "selftests/igt_atomic.h"
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static int igt_global_reset(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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unsigned int reset_count;
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int err = 0;
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/* Check that we can issue a global GPU reset */
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igt_global_reset_lock(i915);
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reset_count = i915_reset_count(&i915->gpu_error);
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i915_reset(i915, ALL_ENGINES, NULL);
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if (i915_reset_count(&i915->gpu_error) == reset_count) {
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pr_err("No GPU reset recorded!\n");
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err = -EINVAL;
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}
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igt_global_reset_unlock(i915);
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if (i915_reset_failed(i915))
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err = -EIO;
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return err;
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}
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static int igt_wedged_reset(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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intel_wakeref_t wakeref;
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/* Check that we can recover a wedged device with a GPU reset */
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igt_global_reset_lock(i915);
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wakeref = intel_runtime_pm_get(i915);
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i915_gem_set_wedged(i915);
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GEM_BUG_ON(!i915_reset_failed(i915));
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i915_reset(i915, ALL_ENGINES, NULL);
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intel_runtime_pm_put(i915, wakeref);
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igt_global_reset_unlock(i915);
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return i915_reset_failed(i915) ? -EIO : 0;
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}
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static int igt_atomic_reset(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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const typeof(*igt_atomic_phases) *p;
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int err = 0;
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/* Check that the resets are usable from atomic context */
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igt_global_reset_lock(i915);
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mutex_lock(&i915->drm.struct_mutex);
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/* Flush any requests before we get started and check basics */
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if (!igt_force_reset(i915))
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goto unlock;
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for (p = igt_atomic_phases; p->name; p++) {
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GEM_TRACE("intel_gpu_reset under %s\n", p->name);
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p->critical_section_begin();
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err = intel_gpu_reset(i915, ALL_ENGINES);
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p->critical_section_end();
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if (err) {
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pr_err("intel_gpu_reset failed under %s\n", p->name);
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break;
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}
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}
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/* As we poke around the guts, do a full reset before continuing. */
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igt_force_reset(i915);
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unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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igt_global_reset_unlock(i915);
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return err;
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}
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int intel_reset_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(igt_global_reset), /* attempt to recover GPU first */
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SUBTEST(igt_wedged_reset),
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SUBTEST(igt_atomic_reset),
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};
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intel_wakeref_t wakeref;
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int err = 0;
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if (!intel_has_gpu_reset(i915))
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return 0;
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if (i915_terminally_wedged(i915))
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return -EIO; /* we're long past hope of a successful reset */
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with_intel_runtime_pm(i915, wakeref)
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err = i915_subtests(tests, i915);
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return err;
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}
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