mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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37a298fb6a
Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
169 lines
4.4 KiB
C
169 lines
4.4 KiB
C
/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
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#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
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enum {
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L_7X30_NONE_CLK = -1,
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L_7X30_ADM_CLK,
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L_7X30_I2C_CLK,
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L_7X30_I2C_2_CLK,
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L_7X30_QUP_I2C_CLK,
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L_7X30_UART1DM_CLK,
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L_7X30_UART1DM_P_CLK,
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L_7X30_UART2DM_CLK,
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L_7X30_UART2DM_P_CLK,
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L_7X30_EMDH_CLK,
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L_7X30_EMDH_P_CLK,
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L_7X30_PMDH_CLK,
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L_7X30_PMDH_P_CLK,
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L_7X30_GRP_2D_CLK,
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L_7X30_GRP_2D_P_CLK,
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L_7X30_GRP_3D_SRC_CLK,
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L_7X30_GRP_3D_CLK,
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L_7X30_GRP_3D_P_CLK,
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L_7X30_IMEM_CLK,
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L_7X30_SDC1_CLK,
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L_7X30_SDC1_P_CLK,
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L_7X30_SDC2_CLK,
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L_7X30_SDC2_P_CLK,
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L_7X30_SDC3_CLK,
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L_7X30_SDC3_P_CLK,
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L_7X30_SDC4_CLK,
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L_7X30_SDC4_P_CLK,
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L_7X30_MDP_CLK,
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L_7X30_MDP_P_CLK,
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L_7X30_MDP_LCDC_PCLK_CLK,
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L_7X30_MDP_LCDC_PAD_PCLK_CLK,
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L_7X30_MDP_VSYNC_CLK,
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L_7X30_MI2S_CODEC_RX_M_CLK,
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L_7X30_MI2S_CODEC_RX_S_CLK,
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L_7X30_MI2S_CODEC_TX_M_CLK,
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L_7X30_MI2S_CODEC_TX_S_CLK,
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L_7X30_MI2S_M_CLK,
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L_7X30_MI2S_S_CLK,
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L_7X30_LPA_CODEC_CLK,
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L_7X30_LPA_CORE_CLK,
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L_7X30_LPA_P_CLK,
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L_7X30_MIDI_CLK,
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L_7X30_MDC_CLK,
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L_7X30_ROTATOR_IMEM_CLK,
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L_7X30_ROTATOR_P_CLK,
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L_7X30_SDAC_M_CLK,
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L_7X30_SDAC_CLK,
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L_7X30_UART1_CLK,
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L_7X30_UART2_CLK,
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L_7X30_UART3_CLK,
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L_7X30_TV_CLK,
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L_7X30_TV_DAC_CLK,
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L_7X30_TV_ENC_CLK,
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L_7X30_HDMI_CLK,
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L_7X30_TSIF_REF_CLK,
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L_7X30_TSIF_P_CLK,
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L_7X30_USB_HS_SRC_CLK,
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L_7X30_USB_HS_CLK,
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L_7X30_USB_HS_CORE_CLK,
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L_7X30_USB_HS_P_CLK,
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L_7X30_USB_HS2_CLK,
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L_7X30_USB_HS2_CORE_CLK,
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L_7X30_USB_HS2_P_CLK,
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L_7X30_USB_HS3_CLK,
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L_7X30_USB_HS3_CORE_CLK,
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L_7X30_USB_HS3_P_CLK,
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L_7X30_VFE_CLK,
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L_7X30_VFE_P_CLK,
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L_7X30_VFE_MDC_CLK,
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L_7X30_VFE_CAMIF_CLK,
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L_7X30_CAMIF_PAD_P_CLK,
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L_7X30_CAM_M_CLK,
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L_7X30_JPEG_CLK,
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L_7X30_JPEG_P_CLK,
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L_7X30_VPE_CLK,
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L_7X30_MFC_CLK,
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L_7X30_MFC_DIV2_CLK,
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L_7X30_MFC_P_CLK,
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L_7X30_SPI_CLK,
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L_7X30_SPI_P_CLK,
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L_7X30_CSI0_CLK,
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L_7X30_CSI0_VFE_CLK,
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L_7X30_CSI0_P_CLK,
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L_7X30_CSI1_CLK,
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L_7X30_CSI1_VFE_CLK,
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L_7X30_CSI1_P_CLK,
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L_7X30_GLBL_ROOT_CLK,
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L_7X30_AXI_LI_VG_CLK,
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L_7X30_AXI_LI_GRP_CLK,
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L_7X30_AXI_LI_JPEG_CLK,
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L_7X30_AXI_GRP_2D_CLK,
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L_7X30_AXI_MFC_CLK,
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L_7X30_AXI_VPE_CLK,
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L_7X30_AXI_LI_VFE_CLK,
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L_7X30_AXI_LI_APPS_CLK,
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L_7X30_AXI_MDP_CLK,
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L_7X30_AXI_IMEM_CLK,
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L_7X30_AXI_LI_ADSP_A_CLK,
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L_7X30_AXI_ROTATOR_CLK,
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L_7X30_NR_CLKS
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};
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struct clk_ops;
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extern struct clk_ops clk_ops_7x30;
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struct clk_ops *clk_7x30_is_local(uint32_t id);
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int clk_7x30_init(void);
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void pll_enable(uint32_t pll);
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void pll_disable(uint32_t pll);
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extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
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#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \
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.name = clk_name, \
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.id = L_7X30_##clk_id, \
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.remote_id = P_##clk_id, \
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.flags = clk_flags, \
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.dev = clk_dev, \
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.dbg_name = #clk_id, \
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}
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#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \
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.name = clk_name, \
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.id = L_7X30_##l_id, \
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.remote_id = P_##r_id, \
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.flags = clk_flags, \
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.dev = clk_dev, \
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.dbg_name = #l_id, \
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}
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#endif
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