Eric Anholt f61145f1a4 drm/vc4: Flush the caches before the bin jobs, as well. ... If the frame samples from a render target that was just written, its cache flush during the binning step may have occurred before the previous frame's RCL was completed. Flush the texture caches again before starting each RCL job to make sure that the sampling of the previous RCL's output is correct. Fixes flickering in the top left of 3DMMES Taiji. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: ca26d28bba ("drm/vc4: improve throughput by pipelining binning and rendering jobs") Link: https://patchwork.freedesktop.org/patch/msgid/20171221221722.23809-1-eric@anholt.net Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>		2018-01-18 12:17:03 -08:00
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drm	drm/vc4: Flush the caches before the bin jobs, as well.	2018-01-18 12:17:03 -08:00
host1x	main drm pull request for v4.15	2017-11-15 20:42:10 -08:00
ipu-v3	fixes/cleanups for rc1, non-desktop flags for VR	2017-11-23 21:04:56 -10:00
vga	vgaarb: Factor out EFI and fallback default device selection	2017-10-18 10:04:56 +02:00
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