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f940f52898
THP code does PTE page allocation along with large page request and deposit them for later use. This is to ensure that we won't have any failures when we split hugepages to regular pages. On powerpc we want to use the deposited PTE page for storing hash pte slot and secondary bit information for the HPTEs. We use the second half of the pmd table to save the deposted PTE page. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H
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#define _ASM_POWERPC_PGTABLE_PPC64_64K_H
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#include <asm-generic/pgtable-nopud.h>
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#define PTE_INDEX_SIZE 8
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#define PMD_INDEX_SIZE 10
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#define PUD_INDEX_SIZE 0
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#define PGD_INDEX_SIZE 12
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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#endif /* __ASSEMBLY__ */
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/* With 4k base page size, hugepage PTEs go at the PMD level */
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#define MIN_HUGEPTE_SHIFT PAGE_SHIFT
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Bits to mask out from a PMD to get to the PTE page */
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/* PMDs point to PTE table fragments which are 4K aligned. */
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#define PMD_MASKED_BITS 0xfff
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/* Bits to mask out from a PGD/PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0x1ff
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#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */
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