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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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143470368e
UTMI pads are shared by USB controllers and reset of UTMI pads is shared with the reset of USB1 controller. Currently reset of UTMI pads is done by the EHCI driver and ChipIdea UDC works because EHCI driver always happen to be probed first. Move reset controls from ehci-tegra to tegra-phy in order to resolve the problem. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
93 lines
2.4 KiB
C
93 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __TEGRA_USB_PHY_H
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#define __TEGRA_USB_PHY_H
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/usb/otg.h>
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/*
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* utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers
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* should be set up by clk-tegra, false if by the PHY code
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* has_hostpc: true if the USB controller has the HOSTPC extension, which
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* changes the location of the PHCD and PTS fields
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* requires_usbmode_setup: true if the USBMODE register needs to be set to
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* enter host mode
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* requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
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* and hsdiscon_level should be set for adequate signal quality
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*/
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struct tegra_phy_soc_config {
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bool utmi_pll_config_in_car_module;
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bool has_hostpc;
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bool requires_usbmode_setup;
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bool requires_extra_tuning_parameters;
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};
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struct tegra_utmip_config {
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u8 hssync_start_delay;
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u8 elastic_limit;
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u8 idle_wait_delay;
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u8 term_range_adj;
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bool xcvr_setup_use_fuses;
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u8 xcvr_setup;
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u8 xcvr_lsfslew;
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u8 xcvr_lsrslew;
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u8 xcvr_hsslew;
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u8 hssquelch_level;
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u8 hsdiscon_level;
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};
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enum tegra_usb_phy_port_speed {
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TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
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TEGRA_USB_PHY_PORT_SPEED_LOW,
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TEGRA_USB_PHY_PORT_SPEED_HIGH,
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};
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struct tegra_xtal_freq;
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struct tegra_usb_phy {
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int instance;
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const struct tegra_xtal_freq *freq;
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void __iomem *regs;
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void __iomem *pad_regs;
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struct clk *clk;
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struct clk *pll_u;
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struct clk *pad_clk;
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struct regulator *vbus;
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enum usb_dr_mode mode;
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void *config;
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const struct tegra_phy_soc_config *soc_config;
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struct usb_phy *ulpi;
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struct usb_phy u_phy;
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bool is_legacy_phy;
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bool is_ulpi_phy;
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int reset_gpio;
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struct reset_control *pad_rst;
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};
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void tegra_usb_phy_preresume(struct usb_phy *phy);
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void tegra_usb_phy_postresume(struct usb_phy *phy);
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void tegra_ehci_phy_restore_start(struct usb_phy *phy,
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enum tegra_usb_phy_port_speed port_speed);
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void tegra_ehci_phy_restore_end(struct usb_phy *phy);
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#endif /* __TEGRA_USB_PHY_H */
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