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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bdae44705c
There is a copy-paste error in the display pipeline device tree graph. The remote endpoint of the display backend 1's output to TCON0 points to the wrong endpoint. This will result in the driver incorrectly parsing the relationship of the components. Reported-by: Andrea Venturi <ennesimamail.av@gmail.com> Fixes:0df4cf33a5("ARM: dts: sun4i: Add device nodes for display pipelines") Fixes:5b92b29bed("ARM: dts: sun7i: Add device nodes for display pipelines") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
1417 lines
34 KiB
Plaintext
1417 lines
34 KiB
Plaintext
/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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aliases {
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ethernet0 = &gmac;
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
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<&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
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<&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
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<&ccu CLK_HDMI>;
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status = "disabled";
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};
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framebuffer@1 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
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<&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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framebuffer@2 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-tve0";
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clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
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<&ccu CLK_AHB_DE_BE0>,
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<&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
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<&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&ccu CLK_CPU>;
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
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960000 1400000
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912000 1400000
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864000 1300000
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720000 1200000
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528000 1100000
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312000 1000000
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144000 1000000
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <6>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&rtp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: clk@1c20050 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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/*
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* The following two are dummy clocks, placeholders
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* used in the gmac_tx clock. The gmac driver will
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* choose one parent depending on the PHY interface
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* mode, using clk_set_rate auto-reparenting.
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*
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* The actual TX clock rate is not controlled by the
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* gmac_tx clock.
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*/
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mii_phy_tx_clk: clk@1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "mii_phy_tx";
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};
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gmac_int_tx_clk: clk@2 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "gmac_int_tx";
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};
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gmac_tx_clk: clk@1c20164 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-gmac-clk";
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reg = <0x01c20164 0x4>;
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clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
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clock-output-names = "gmac_tx";
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};
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};
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de: display-engine {
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compatible = "allwinner,sun7i-a20-display-engine";
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allwinner,pipelines = <&fe0>, <&fe1>;
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status = "disabled";
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};
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soc@1c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram-controller@1c00000 {
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compatible = "allwinner,sun4i-a10-sram-controller";
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reg = <0x01c00000 0x30>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_a: sram@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 0xc000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00000000 0xc000>;
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emac_sram: sram-section@8000 {
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compatible = "allwinner,sun4i-a10-sram-a3-a4";
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reg = <0x8000 0x4000>;
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status = "disabled";
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};
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};
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sram_d: sram@10000 {
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compatible = "mmio-sram";
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reg = <0x00010000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00010000 0x1000>;
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otg_sram: sram-section@0 {
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compatible = "allwinner,sun4i-a10-sram-d";
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reg = <0x0000 0x1000>;
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status = "disabled";
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};
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};
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};
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nmi_intc: interrupt-controller@1c00030 {
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compatible = "allwinner,sun7i-a20-sc-nmi";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x01c00030 0x0c>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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dma: dma-controller@1c02000 {
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compatible = "allwinner,sun4i-a10-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_DMA>;
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#dma-cells = <2>;
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};
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nfc: nand@1c03000 {
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compatible = "allwinner,sun4i-a10-nand";
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reg = <0x01c03000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 3>;
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dma-names = "rxtx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@1c05000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c05000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 27>,
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<&dma SUN4I_DMA_DEDICATED 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <4>;
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};
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spi1: spi@1c06000 {
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compatible = "allwinner,sun4i-a10-spi";
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reg = <0x01c06000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
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clock-names = "ahb", "mod";
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dmas = <&dma SUN4I_DMA_DEDICATED 9>,
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<&dma SUN4I_DMA_DEDICATED 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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};
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emac: ethernet@1c0b000 {
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compatible = "allwinner,sun4i-a10-emac";
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reg = <0x01c0b000 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB_EMAC>;
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allwinner,sram = <&emac_sram 1>;
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status = "disabled";
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};
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mdio: mdio@1c0b080 {
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compatible = "allwinner,sun4i-a10-mdio";
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reg = <0x01c0b080 0x14>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tcon0: lcd-controller@1c0c000 {
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compatible = "allwinner,sun7i-a20-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_TCON0>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB_LCD0>,
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<&ccu CLK_TCON0_CH0>,
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<&ccu CLK_TCON0_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon0-pixel-clock";
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dmas = <&dma SUN4I_DMA_DEDICATED 14>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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tcon0_in_be1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&be1_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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tcon0_out_hdmi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&hdmi_in_tcon0>;
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allwinner,tcon-channel = <1>;
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};
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};
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};
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};
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tcon1: lcd-controller@1c0d000 {
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compatible = "allwinner,sun7i-a20-tcon";
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reg = <0x01c0d000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_TCON1>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB_LCD1>,
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<&ccu CLK_TCON1_CH0>,
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<&ccu CLK_TCON1_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon1-pixel-clock";
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dmas = <&dma SUN4I_DMA_DEDICATED 15>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon1_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon1_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon1>;
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};
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tcon1_in_be1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&be1_out_tcon1>;
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};
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};
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tcon1_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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tcon1_out_hdmi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&hdmi_in_tcon1>;
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allwinner,tcon-channel = <1>;
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};
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};
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};
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC0>,
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<&ccu CLK_MMC0>,
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<&ccu CLK_MMC0_OUTPUT>,
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<&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_AHB_MMC1>,
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<&ccu CLK_MMC1>,
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<&ccu CLK_MMC1_OUTPUT>,
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<&ccu CLK_MMC1_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@1c11000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c11000 0x1000>;
|
|
clocks = <&ccu CLK_AHB_MMC2>,
|
|
<&ccu CLK_MMC2>,
|
|
<&ccu CLK_MMC2_OUTPUT>,
|
|
<&ccu CLK_MMC2_SAMPLE>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc3: mmc@1c12000 {
|
|
compatible = "allwinner,sun7i-a20-mmc";
|
|
reg = <0x01c12000 0x1000>;
|
|
clocks = <&ccu CLK_AHB_MMC3>,
|
|
<&ccu CLK_MMC3>,
|
|
<&ccu CLK_MMC3_OUTPUT>,
|
|
<&ccu CLK_MMC3_SAMPLE>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
usb_otg: usb@1c13000 {
|
|
compatible = "allwinner,sun4i-a10-musb";
|
|
reg = <0x01c13000 0x0400>;
|
|
clocks = <&ccu CLK_AHB_OTG>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
extcon = <&usbphy 0>;
|
|
allwinner,sram = <&otg_sram 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: phy@1c13400 {
|
|
#phy-cells = <1>;
|
|
compatible = "allwinner,sun7i-a20-usb-phy";
|
|
reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
|
|
reg-names = "phy_ctrl", "pmu1", "pmu2";
|
|
clocks = <&ccu CLK_USB_PHY>;
|
|
clock-names = "usb_phy";
|
|
resets = <&ccu RST_USB_PHY0>,
|
|
<&ccu RST_USB_PHY1>,
|
|
<&ccu RST_USB_PHY2>;
|
|
reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci0: usb@1c14000 {
|
|
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
|
|
reg = <0x01c14000 0x100>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_EHCI0>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@1c14400 {
|
|
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
|
|
reg = <0x01c14400 0x100>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
crypto: crypto-engine@1c15000 {
|
|
compatible = "allwinner,sun7i-a20-crypto",
|
|
"allwinner,sun4i-a10-crypto";
|
|
reg = <0x01c15000 0x1000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
|
|
clock-names = "ahb", "mod";
|
|
};
|
|
|
|
hdmi: hdmi@1c16000 {
|
|
compatible = "allwinner,sun7i-a20-hdmi",
|
|
"allwinner,sun5i-a10s-hdmi";
|
|
reg = <0x01c16000 0x1000>;
|
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
|
|
<&ccu CLK_PLL_VIDEO0_2X>,
|
|
<&ccu CLK_PLL_VIDEO1_2X>;
|
|
clock-names = "ahb", "mod", "pll-0", "pll-1";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 16>,
|
|
<&dma SUN4I_DMA_NORMAL 16>,
|
|
<&dma SUN4I_DMA_DEDICATED 24>;
|
|
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hdmi_in: port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
hdmi_in_tcon0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon0_out_hdmi>;
|
|
};
|
|
|
|
hdmi_in_tcon1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&tcon1_out_hdmi>;
|
|
};
|
|
};
|
|
|
|
hdmi_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
spi2: spi@1c17000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c17000 0x1000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
|
<&dma SUN4I_DMA_DEDICATED 28>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
num-cs = <1>;
|
|
};
|
|
|
|
ahci: sata@1c18000 {
|
|
compatible = "allwinner,sun4i-a10-ahci";
|
|
reg = <0x01c18000 0x1000>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@1c1c000 {
|
|
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
|
|
reg = <0x01c1c000 0x100>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_EHCI1>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@1c1c400 {
|
|
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
|
|
reg = <0x01c1c400 0x100>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@1c1f000 {
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
reg = <0x01c1f000 0x1000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 31>,
|
|
<&dma SUN4I_DMA_DEDICATED 30>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
num-cs = <1>;
|
|
};
|
|
|
|
ccu: clock@1c20000 {
|
|
compatible = "allwinner,sun7i-a20-ccu";
|
|
reg = <0x01c20000 0x400>;
|
|
clocks = <&osc24M>, <&osc32k>;
|
|
clock-names = "hosc", "losc";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pio: pinctrl@1c20800 {
|
|
compatible = "allwinner,sun7i-a20-pinctrl";
|
|
reg = <0x01c20800 0x400>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
can0_pins_a: can0@0 {
|
|
pins = "PH20", "PH21";
|
|
function = "can";
|
|
};
|
|
|
|
clk_out_a_pins_a: clk_out_a@0 {
|
|
pins = "PI12";
|
|
function = "clk_out_a";
|
|
};
|
|
|
|
clk_out_b_pins_a: clk_out_b@0 {
|
|
pins = "PI13";
|
|
function = "clk_out_b";
|
|
};
|
|
|
|
emac_pins_a: emac0@0 {
|
|
pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
"PA15", "PA16";
|
|
function = "emac";
|
|
};
|
|
|
|
gmac_pins_mii_a: gmac_mii@0 {
|
|
pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
"PA15", "PA16";
|
|
function = "gmac";
|
|
};
|
|
|
|
gmac_pins_rgmii_a: gmac_rgmii@0 {
|
|
pins = "PA0", "PA1", "PA2",
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
"PA7", "PA8", "PA10",
|
|
"PA11", "PA12", "PA13",
|
|
"PA15", "PA16";
|
|
function = "gmac";
|
|
/*
|
|
* data lines in RGMII mode use DDR mode
|
|
* and need a higher signal drive strength
|
|
*/
|
|
drive-strength = <40>;
|
|
};
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
pins = "PB0", "PB1";
|
|
function = "i2c0";
|
|
};
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
pins = "PB18", "PB19";
|
|
function = "i2c1";
|
|
};
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
pins = "PB20", "PB21";
|
|
function = "i2c2";
|
|
};
|
|
|
|
i2c3_pins_a: i2c3@0 {
|
|
pins = "PI0", "PI1";
|
|
function = "i2c3";
|
|
};
|
|
|
|
ir0_rx_pins_a: ir0@0 {
|
|
pins = "PB4";
|
|
function = "ir0";
|
|
};
|
|
|
|
ir0_tx_pins_a: ir0@1 {
|
|
pins = "PB3";
|
|
function = "ir0";
|
|
};
|
|
|
|
ir1_rx_pins_a: ir1@0 {
|
|
pins = "PB23";
|
|
function = "ir1";
|
|
};
|
|
|
|
ir1_tx_pins_a: ir1@1 {
|
|
pins = "PB22";
|
|
function = "ir1";
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
pins = "PF0", "PF1", "PF2",
|
|
"PF3", "PF4", "PF5";
|
|
function = "mmc0";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
mmc2_pins_a: mmc2@0 {
|
|
pins = "PC6", "PC7", "PC8",
|
|
"PC9", "PC10", "PC11";
|
|
function = "mmc2";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
mmc3_pins_a: mmc3@0 {
|
|
pins = "PI4", "PI5", "PI6",
|
|
"PI7", "PI8", "PI9";
|
|
function = "mmc3";
|
|
drive-strength = <30>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
ps20_pins_a: ps20@0 {
|
|
pins = "PI20", "PI21";
|
|
function = "ps2";
|
|
};
|
|
|
|
ps21_pins_a: ps21@0 {
|
|
pins = "PH12", "PH13";
|
|
function = "ps2";
|
|
};
|
|
|
|
pwm0_pins_a: pwm0@0 {
|
|
pins = "PB2";
|
|
function = "pwm";
|
|
};
|
|
|
|
pwm1_pins_a: pwm1@0 {
|
|
pins = "PI3";
|
|
function = "pwm";
|
|
};
|
|
|
|
spdif_tx_pins_a: spdif@0 {
|
|
pins = "PB13";
|
|
function = "spdif";
|
|
bias-pull-up;
|
|
};
|
|
|
|
spi0_pins_a: spi0@0 {
|
|
pins = "PI11", "PI12", "PI13";
|
|
function = "spi0";
|
|
};
|
|
|
|
spi0_cs0_pins_a: spi0_cs0@0 {
|
|
pins = "PI10";
|
|
function = "spi0";
|
|
};
|
|
|
|
spi0_cs1_pins_a: spi0_cs1@0 {
|
|
pins = "PI14";
|
|
function = "spi0";
|
|
};
|
|
|
|
spi1_pins_a: spi1@0 {
|
|
pins = "PI17", "PI18", "PI19";
|
|
function = "spi1";
|
|
};
|
|
|
|
spi1_cs0_pins_a: spi1_cs0@0 {
|
|
pins = "PI16";
|
|
function = "spi1";
|
|
};
|
|
|
|
spi2_pins_a: spi2@0 {
|
|
pins = "PC20", "PC21", "PC22";
|
|
function = "spi2";
|
|
};
|
|
|
|
spi2_pins_b: spi2@1 {
|
|
pins = "PB15", "PB16", "PB17";
|
|
function = "spi2";
|
|
};
|
|
|
|
spi2_cs0_pins_a: spi2_cs0@0 {
|
|
pins = "PC19";
|
|
function = "spi2";
|
|
};
|
|
|
|
spi2_cs0_pins_b: spi2_cs0@1 {
|
|
pins = "PB14";
|
|
function = "spi2";
|
|
};
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
pins = "PB22", "PB23";
|
|
function = "uart0";
|
|
};
|
|
|
|
uart2_pins_a: uart2@0 {
|
|
pins = "PI16", "PI17", "PI18", "PI19";
|
|
function = "uart2";
|
|
};
|
|
|
|
uart3_pins_a: uart3@0 {
|
|
pins = "PG6", "PG7", "PG8", "PG9";
|
|
function = "uart3";
|
|
};
|
|
|
|
uart3_pins_b: uart3@1 {
|
|
pins = "PH0", "PH1";
|
|
function = "uart3";
|
|
};
|
|
|
|
uart4_pins_a: uart4@0 {
|
|
pins = "PG10", "PG11";
|
|
function = "uart4";
|
|
};
|
|
|
|
uart4_pins_b: uart4@1 {
|
|
pins = "PH4", "PH5";
|
|
function = "uart4";
|
|
};
|
|
|
|
uart5_pins_a: uart5@0 {
|
|
pins = "PI10", "PI11";
|
|
function = "uart5";
|
|
};
|
|
|
|
uart6_pins_a: uart6@0 {
|
|
pins = "PI12", "PI13";
|
|
function = "uart6";
|
|
};
|
|
|
|
uart7_pins_a: uart7@0 {
|
|
pins = "PI20", "PI21";
|
|
function = "uart7";
|
|
};
|
|
};
|
|
|
|
timer@1c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0x90>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt: watchdog@1c20c90 {
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
|
reg = <0x01c20c90 0x10>;
|
|
};
|
|
|
|
rtc: rtc@1c20d00 {
|
|
compatible = "allwinner,sun7i-a20-rtc";
|
|
reg = <0x01c20d00 0x20>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pwm: pwm@1c20e00 {
|
|
compatible = "allwinner,sun7i-a20-pwm";
|
|
reg = <0x01c20e00 0xc>;
|
|
clocks = <&osc24M>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif: spdif@1c21000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-spdif";
|
|
reg = <0x01c21000 0x400>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
|
|
clock-names = "apb", "spdif";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 2>,
|
|
<&dma SUN4I_DMA_NORMAL 2>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ir0: ir@1c21800 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x01c21800 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ir1: ir@1c21c00 {
|
|
compatible = "allwinner,sun4i-a10-ir";
|
|
clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
|
|
clock-names = "apb", "ir";
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x01c21c00 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: i2s@1c22000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-i2s";
|
|
reg = <0x01c22000 0x400>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 4>,
|
|
<&dma SUN4I_DMA_NORMAL 4>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s0: i2s@1c22400 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-i2s";
|
|
reg = <0x01c22400 0x400>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 3>,
|
|
<&dma SUN4I_DMA_NORMAL 3>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
lradc: lradc@1c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
codec: codec@1c22c00 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun7i-a20-codec";
|
|
reg = <0x01c22c00 0x40>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
|
|
clock-names = "apb", "codec";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 19>,
|
|
<&dma SUN4I_DMA_NORMAL 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
sid: eeprom@1c23800 {
|
|
compatible = "allwinner,sun7i-a20-sid";
|
|
reg = <0x01c23800 0x200>;
|
|
};
|
|
|
|
i2s2: i2s@1c24400 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-i2s";
|
|
reg = <0x01c24400 0x400>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma SUN4I_DMA_NORMAL 6>,
|
|
<&dma SUN4I_DMA_NORMAL 6>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtp: rtp@1c25000 {
|
|
compatible = "allwinner,sun5i-a13-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@1c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@1c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@1c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@1c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@1c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@1c29400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29400 0x400>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@1c29800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29800 0x400>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@1c29c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29c00 0x400>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_APB1_UART7>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ps20: ps2@1c2a000 {
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
reg = <0x01c2a000 0x400>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_PS20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ps21: ps2@1c2a400 {
|
|
compatible = "allwinner,sun4i-a10-ps2";
|
|
reg = <0x01c2a400 0x400>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_PS21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@1c2ac00 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_I2C0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@1c2b000 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_I2C1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@1c2b400 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_I2C2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c@1c2b800 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2b800 0x400>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_I2C3>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
can0: can@1c2bc00 {
|
|
compatible = "allwinner,sun7i-a20-can",
|
|
"allwinner,sun4i-a10-can";
|
|
reg = <0x01c2bc00 0x400>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_CAN>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@1c2c000 {
|
|
compatible = "allwinner,sun7i-a20-i2c",
|
|
"allwinner,sun4i-a10-i2c";
|
|
reg = <0x01c2c000 0x400>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_APB1_I2C4>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gmac: ethernet@1c50000 {
|
|
compatible = "allwinner,sun7i-a20-gmac";
|
|
reg = <0x01c50000 0x10000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
|
|
clock-names = "stmmaceth", "allwinner_gmac_tx";
|
|
snps,pbl = <2>;
|
|
snps,fixed-burst;
|
|
snps,force_sf_dma_mode;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
hstimer@1c60000 {
|
|
compatible = "allwinner,sun7i-a20-hstimer";
|
|
reg = <0x01c60000 0x1000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_HSTIMER>;
|
|
};
|
|
|
|
gic: interrupt-controller@1c81000 {
|
|
compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x2000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
fe0: display-frontend@1e00000 {
|
|
compatible = "allwinner,sun7i-a20-display-frontend";
|
|
reg = <0x01e00000 0x20000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
|
|
<&ccu CLK_DRAM_DE_FE0>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_FE0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fe0_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
fe0_out_be0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&be0_in_fe0>;
|
|
};
|
|
|
|
fe0_out_be1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&be1_in_fe0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
fe1: display-frontend@1e20000 {
|
|
compatible = "allwinner,sun7i-a20-display-frontend";
|
|
reg = <0x01e20000 0x20000>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
|
|
<&ccu CLK_DRAM_DE_FE1>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_FE1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fe1_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
fe1_out_be0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&be0_in_fe1>;
|
|
};
|
|
|
|
fe1_out_be1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&be1_in_fe1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
be1: display-backend@1e40000 {
|
|
compatible = "allwinner,sun7i-a20-display-backend";
|
|
reg = <0x01e40000 0x10000>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
|
|
<&ccu CLK_DRAM_DE_BE1>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_BE1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
be1_in: port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
be1_in_fe0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&fe0_out_be1>;
|
|
};
|
|
|
|
be1_in_fe1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&fe1_out_be1>;
|
|
};
|
|
};
|
|
|
|
be1_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
be1_out_tcon0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon0_in_be1>;
|
|
};
|
|
|
|
be1_out_tcon1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&tcon1_in_be1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
be0: display-backend@1e60000 {
|
|
compatible = "allwinner,sun7i-a20-display-backend";
|
|
reg = <0x01e60000 0x10000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
|
|
<&ccu CLK_DRAM_DE_BE0>;
|
|
clock-names = "ahb", "mod",
|
|
"ram";
|
|
resets = <&ccu RST_DE_BE0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
be0_in: port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
be0_in_fe0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&fe0_out_be0>;
|
|
};
|
|
|
|
be0_in_fe1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&fe1_out_be0>;
|
|
};
|
|
};
|
|
|
|
be0_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
be0_out_tcon0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon0_in_be0>;
|
|
};
|
|
|
|
be0_out_tcon1: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&tcon1_in_be0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|